A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

Abstract

Reversible logic has been emerging as a replacement for conventional digital computers and has been found to be a promising technology for the future that can improve the quality of circuits in terms of power, speed, heat dissipation, life span, and input traceability. The new generation of quantum processors demands the efficient implementation of decimal data path elements in many commercial, financial, and Internet-based applications. Reversible binary-coded decimal multipliers are among the important circuits in quantum computers. In this approach, we propose a low-power reversible radix binary-coded decimal multiplier. The proposed methodology uses a novel 4221 reversible recorder gate to select precomputed constant multiples and binary to excess-six conversion reversible decimal adder for partial product compression. The proposed multiplier is designed with 180-nm application-specific integrated circuit technology using the Cadence EDA tool and is compared with state-of-the-art BCD algorithms designed using reversible gates. Experimental evaluations revealed that the proposed design demonstrates power and power-delay product reductions of 28% and 37%, respectively, compared to those of the best BCD algorithms implemented in reversible logic.