Readout Application Specific Integrated Circuit Research Articles

Ultrasonic Fingerprint Sensor With Transmit Beamforming Based on a PMUT Array Bonded to CMOS Circuitry.

In this paper, we present a single-chip 65 ×42 element ultrasonic pulse-echo fingerprint sensor with transmit (TX) beamforming based on piezoelectric micromachined ultrasonic transducers directly bonded to a CMOS readout application-specific integrated circuit (ASIC). The readout ASIC was realized in a standard 180-nm CMOS process with a 24-V high-voltage transistor option. Pulse-echo measurements are performed column-by-column in sequence using either one column or five columns to TX the ultrasonic pulse at 20 MHz. TX beamforming is used to focus the ultrasonic beam at the imaging plane where the finger is located, increasing the ultrasonic pressure and narrowing the 3-dB beamwidth to [Formula: see text], a factor of 6.4 narrower than nonbeamformed measurements. The surface of the sensor is coated with a poly-dimethylsiloxane (PDMS) layer to provide good acoustic impedance matching to skin. Scanning laser Doppler vibrometry of the PDMS surface was used to map the ultrasonic pressure field at the imaging surface, demonstrating the expected increase in pressure, and reduction in beamwidth. Imaging experiments were conducted using both PDMS phantoms and real fingerprints. The average image contrast is increased by a factor of 1.5 when beamforming is used.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35µm CMOS process with a die size of 2.60mm×3.53mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e−+16.3e−/pF with a power consumption of 4mW and achieves a conversion gain of 87mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975keV (FWHM) for gamma rays of 59.5keV was measured by connecting the ASIC to a 5mm×5mm ×2mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors**Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e− at zero farad plus 8.2 e− per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta \Sigma {\text{ADC}}$&lt;/tex-math&gt; &lt;/inline-formula&gt;

A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma ( $\Delta \Sigma $ ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the $\Sigma \Delta{\rm ADC}$ instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in $0.35 \upmu\hbox{m}$ CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with $35.1 \pm 0.3 \upmu\hbox{V}$ input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being $4 \upmu\hbox{V}/\hbox{e}^-$ . The integration test results show that the readout noise is $11.8 \hbox{e}^ {-} $ at 100 kHz readout pixel rate and the achieved energy spectrum resolution is $168 \hbox{eV} \pm 4.7 \hbox{eV}$ (Full Width at Half Maximum: FWHM) at 5.9 keV.

Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

X-ray characterization of a multichannel smart-pixel array detector.

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 × 48 pixels, each 130 µm × 130 µm × 520 µm thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

A Circadian and Cardiac Intraocular Pressure Sensor for Smart Implantable Lens.

This paper presents a new system to measure the Intraocular Pressure (IOP) with very high accuracy (0.036 mbar) used for monitoring glaucoma. The system not only monitors the daily variation of the IOP (circadian IOP), but also allows to perform an spectral analysis of the pressure signal generated by the heartbeat (cardiac IOP). The system comprises a piezoresistive pressure sensor, an application-specific integrated circuit (ASIC) to read out the sensor data and an external reader installed on customized glasses. The ASIC readout electronics combines chopping modulation with correlated double sampling (CDS) in order to eliminate both the amplifier offset and the chopper ripple at the sampling frequency. In addition, programmable current sources are used to compensate for the atmospheric pressure ( 800-1200 mbar ) and the circadian component (± 7 mbar) thus allowing to read out the very weak cardiac signals (± 1.6 mbar) with a maximum accuracy of 0.036 mbar.

Design and performance of a 16-channel radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

This paper presents the design and the performance of a low-noise front-end readout application specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager. A cascode amplifier based on split-let topology is proposed to realize the charge-sensitive amplifier (CSA) for the sake of a single positive power supply. A leakage-current-compensation circuit is added to suppress the maximum leakage current of 10nA. The output of the CSA is connected to a CR–RC shaper. In the timing branch, the output of the CSA is followed by a fast shaper for the trigger acquisition. A digital monostable circuit is designed to adjust the delay of trigger signals so that the peak value of the shaped voltage signals can be tracked. The sampled voltages are stored into an analog memory. A radiation-hardened-by-design methodology is proposed to achieve the radiation hardness for the space applications. A 16-channel front-end readout ASIC is designed and implemented in TSMC 0.35μm CMOS process. The die size is 2.12mm×4.60mm. The input range of the ASIC is from 4k e− to 140k e−, which is suitable for the detection of the gamma ray from 20keV to 650keV. The ASIC has been tested. The gain of the readout channel is typically 81.4mV/fC. The equivalent noise charge (ENC) is 50 e− at zero farad plus 18 e− per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The static power dissipation is about 16.5mW plus 10.6mW/channel. In addition, the tested results show that the proposed ASIC can resist larger than 200krad(Si) TID irradiation.

Development of a Detector for Gamma-Ray Spectroscopy Based on Silicon Drift Detector Arrays and 2&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${^\prime}{^\prime}$&lt;/tex&gt; &lt;/formula&gt; Lanthanum Bromide Scintillator

This work describes the development of a gamma detector based on silicon drift detectors (SDDs) to read out large ${\hbox{LaBr}}_3$ : ${\hbox{Ce}}$ scintillators for gamma-ray astronomy applications, within an activity supported by the European Space Agency (ESA). SDDs, characterized by high quantum efficiency and low electronic noise, when coupled with a scintillator are good candidates for gamma-ray spectroscopy applications in a wide energy range, e.g., from 150 keV to 15 MeV. The gamma-ray detector prototype presented here is composed of a 2 ${^\prime}{^\prime}$ $\times$ 2 ${^\prime}{^\prime}$ ${\hbox{LaBr}}_3$ : ${\hbox{Ce}}$ scintillator coupled with four SDD arrays arranged in a $2 \times 2$ format (a total of 36 SDDs). This detection system is operated with custom readout application specific integrated circuits (ASICs) and a data acquisition (DAQ) system. With this prototype gamma-camera, an energy resolution of 3.4% FWHM at 662 keV has been measured. Spectroscopy measurements have been carried out between 300 keV and 1800 keV and the achieved results are consistent with the electronic noise of the SDD technology. In this work, we report on the SDD based detection head’s design, its X-ray characterization, readout electronics, experimental setups and gamma-ray spectroscopy results. Finally, perspectives with the possible use of an improved SDD technology are discussed.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

Evaluation of position-estimation methods applied to CZT-based photon-counting detectors for dedicated breast CT

Semiconductor photon-counting detectors based on high atomic number, high density materials [cadmium zinc telluride (CZT)/cadmium telluride (CdTe)] for x-ray computed tomography (CT) provide advantages over conventional energy-integrating detectors, including reduced electronic and Swank noise, wider dynamic range, capability of spectral CT, and improved signal-to-noise ratio. Certain CT applications require high spatial resolution. In breast CT, for example, visualization of microcalcifications and assessment of tumor microvasculature after contrast enhancement require resolution on the order of [Formula: see text]. A straightforward approach to increasing spatial resolution of pixellated CZT-based radiation detectors by merely decreasing the pixel size leads to two problems: (1)fabricating circuitry with small pixels becomes costly and (2)inter-pixel charge spreading can obviate any improvement in spatial resolution. We have used computer simulations to investigate position estimation algorithms that utilize charge sharing to achieve subpixel position resolution. To study these algorithms, we model a simple detector geometry with a [Formula: see text] array of [Formula: see text] pixels, and use a conditional probability function to model charge transport in CZT. We used COMSOL finite element method software to map the distribution of charge pulses and the Monte Carlo package PENELOPE for simulating fluorescent radiation. Performance of two x-ray interaction position estimation algorithms was evaluated: the method of maximum-likelihood estimation and a fast, practical algorithm that can be implemented in a readout application-specific integrated circuit and allows for identification of a quadrant of the pixel in which the interaction occurred. Both methods demonstrate good subpixel resolution; however, their actual efficiency is limited by the presence of fluorescent [Formula: see text]-escape photons. Current experimental breast CT systems typically use detectors with a pixel size of [Formula: see text], with [Formula: see text] binning during the acquisition giving an effective pixel size of [Formula: see text]. Thus, it would be expected that the position estimate accuracy reported in this study would improve detection and visualization of microcalcifications as compared to that with conventional detectors.

Interconnect and bonding techniques for pixelated X-ray and gamma-ray detectors

In the last decade, the Detector Development Group at the Technology Department of the Science and Technology Facilities Council (STFC), U.K., established a variety of fabrication and bonding techniques to build pixelated X-ray and γ-ray detector systems such as the spectroscopic X-ray imaging detector HEXITEC [1]. The fabrication and bonding of such devices comprises a range of processes including material surface preparation, photolithography, stencil printing, flip-chip and wire bonding of detectors to application-specific integrated circuits (ASIC). This paper presents interconnect and bonding techniques used in the fabrication chain for pixelated detectors assembled at STFC. For this purpose, detector dies (∼ 20× 20 mm2) of high quality, single crystal semiconductors, such as cadmium zinc telluride (CZT) are cut to the required thickness (up to 5mm). The die surfaces are lapped and polished to a mirror-finish and then individually processed by electroless gold deposition combined with photolithography to form 74× 74 arrays of 200 μ m × 200 μ m pixels with 250 μ m pitch. Owing to a lack of availability of CZT wafers, lithography is commonly carried out on individual detector dies which represents a significant technical challenge as the edge of the pixel array and the surrounding guard band lies close to the physical edge of the crystal. Further, such detector dies are flip-chip bonded to readout ASIC using low-temperature curing silver-loaded epoxy so that the stress between the bonded detector die and the ASIC is minimized. In addition, this reduces crystalline modifications of the detector die that occur at temperature greater than 150\\r{ }C and have adverse effects on the detector performance. To allow smaller pitch detectors to be bonded, STFC has also developed a compression cold-weld indium bump bonding technique utilising bumps formed by a photolithographic lift-off technique.

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45keV to 281keV. The gain is larger than 100mV/fC. The equivalent noise charge (ENC) of the ASIC is 53e− at zero farad plus 10e− per picofarad. The power dissipation is less than 4.4mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200krad (Si).

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of $1~\hbox{mm}^{3}$ , the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in $0.35~\mu\hbox{m}$ CMOS process. The die size is $2.286~\hbox{mm} \times 2.282~\hbox{mm}$ . The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Prototype characterization of the JUNGFRAU pixel detector for SwissFEL

The SwissFEL, a free electron laser (FEL) based next generation X-ray source, is being built at PSI. An XFEL poses several challenges to the detector development: in particular the single photon counting readout, a successful scheme in case of synchrotron sources, can not be used. At the same time the data quality of photon counting systems, i.e. the low noise and the high dynamic range, is essential from an experimental point of view.Detectors with these features are under development for the EU-XFEL in Hamburg, with the PSI SLS Detector group being involved in one of these efforts (AGIPD). The pulse train time structure of the EU-XFEL machine forces the need of in pixel image storage, resulting in pixel pitches in the 200 μm range. Since the SwissFEL is a 100 Hz repetition rate machine, this constrain is relaxed. For this reason, PSI is developing a 75 μm pitch pixel detector that, thanks to its automatic gain switching technique, will achieve single photon resolution and a high dynamic range. The detector is modular, with each module consisting of a 4 × 8 cm2 active sensor bump bonded to 8 readout ASICs (Application Specific Integrated Circuit), connected to a single printed circuit readout board with 10GbE link capabilities for data download.We have designed and tested a 48 × 48 pixel prototype produced in UMC110 nm technology. In this paper we present the general detector and ASIC design as well as the results of the prototype characterization measurements.

Micron resolution of MÖNCH and GOTTHARD, small pitch charge integrating detectors with single photon sensitivity

MÖNCH, a charge integrating readout ASIC (Application Specific Integrated Circuit) prototypewith a pixel pitch of 25 μm developed at PSI, allows new imagingapplications in the field of micron resolution and spectral imaging.The small pixel size of this system facilitates charge sharing betweenpixels, which then can be exploited to gain additional informationabout the photon absorption position and photon energy.However, for reconstructing complete images from this information,sufficient hits need to be recorded and therefore acquisition timesare potentially long. We present a fast read-out system, that iscapable of acquiring enough statistics for an image in a few hours incombination with a position reconstruction algorithm, which has thepotential to run in a similar amount of time on a fast computing node.We further present results of experiments with a comparable strip detector (small-pitch GOTTHARD system) showing that with the aid of single photon interpolation algorithms micronresolution is achievable. Additionally, we show that a similar position reconstruction algorithm works in the two dimensional case for MÖNCH.

Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35μm CMOS process. The die size is 2.3mm ×2.3mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2keV to 1MeV. The gain of the readout channel is 65mV/fC at the shaping time of 1μs. The best test result of the equivalent noise charge (ENC) is 58.9e− at zero farad plus 5.4e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3mW/channel.

STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has beendesigned to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. Itis dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasoundimaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mmand a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single endedconnection to the SiPM. The time and energy information of the detector signalis encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between thesignal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integratedTDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than285 ps. We present details on the chip design as well as first characterization measurements.