Application Specific Integrated Circuit Design Research Articles

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

In neuromorphic computing, different learning mechanisms are being widely adopted to improve the performance of a specific application. Among these techniques, spike-timing-dependent plasticity (STDP) stands out as one of the most favored. STDP is simply managed by the temporal information of an event, which is biologically inspired. However, most of the prior works on STDP are focused on circuit implementation or software simulation for performance evaluation. Previous works also lack a comparative analysis of the performances of different STDP implementations. This study aims to provide a comprehensive assessment of STDP, centering on the performance across various applications such as classification (static and temporal datasets), control, and reservoir computing. Different applications necessitate distinct STDP configurations to achieve optimal performance with the neuroprocessor. Additionally, this work introduces an application-specific integrated circuit design of STDP circuitry. The design is based on current-controlled memristive synapse principles and utilizes 65 nm CMOS technology from IBM. The detailed presentation includes circuitry specifics, layout, and performance parameters such as energy consumption and design area.

Technology independent optimization when implementing sparse systems of disjunctive normal forms of Boolean functions in ASIC

Objectives. The problem of choosing the best methods and programs for circuit implementation as part of digital ASIC (Application-Specific Integrated Circuit) sparse systems of disjunctive normal forms (DNF) of completely defined Boolean functions is considered. For matrix forms of sparse DNF systems, the ternary matrix specifying elementary conjunctions contains a large proportion of undefined values corresponding to missing literals of Boolean input variables, and the Boolean matrix specifying the occurrences of conjunctions in DNF functions contains a large proportion of zero values.Methods. It is proposed to investigate various methods of technologically independent logical optimization performed at the first stage of logical synthesis: joint minimization of systems of functions in the DNF class, separate and joint minimization in classes of multilevel representations in the form of Boolean networks and BDD representations using mutually inverse cofactors, as well as the division of a system of functions into subsystems with a limited number of input variables and the method of block cover of DNF systems, focused on minimizing the total area of the blocks forming the cover.Results. When implementing sparse DNF systems of Boolean functions in ASIC, along with traditional methods of joint minimization of systems of functions in the DNF class, methods for optimizing multilevel representations of Boolean function systems based on Shannon expansions can be used for technologically independent optimization, while separate minimization and joint minimization of the entire system as a whole turn out to be less effective compared with block partitions and coatings of the DNF system and subsequent minimization of multilevel representations. Schemes obtained as a result of synthesis using minimized representations of Boolean networks often have a smaller area than schemes obtained using minimized BDD representations.Conclusion. For the design of digital ASIC, the effectiveness of combined approach is shown, when initially the block coverage programs of the DNF system is used, followed by the use of programs to minimize multilevel block representations in the form of Boolean networks minimized based on Shannon expansion.

Revolutionizing machine learning: A comprehensive analysis of ASIC hardware accelerators and their applications

The growth of the web over the past few years has led to tremendous data growth, which has provided a powerful impetus for artificial intelligence and machine learning. Machine learning algorithms are widely used in various classification and prediction problems. However, with the rich data types and needs, the traditional software computing method that relies on CPU can no longer meet the application scenarios under different requirements. Machine Learning (ML) hardware accelerators, especially Application Specific Integrated Circuits (ASICs), have become trendy to meet a variety of needs. This paper reviews the research on ML ASIC in the past few years, reviews the development of ML and ASIC design, and summarizes the characteristics of their use. It is followed by examples of various scenarios for which it can be used, such as medical diagnostics and internet of thing (IOT) terminals. Finally, the author analyses the existing problems and limitations, and gives the improvement methods of hardware and algorithm to deal with the related obstacles. It is hoped that this paper can provide some help and convenience for the subsequent related research.

Stochastic Computing Convolutional Neural Network Architecture Reinvented for Highly Efficient Artificial Intelligence Workload on Field-Programmable Gate Array.

Stochastic computing (SC) has a substantial amount of study on application-specific integrated circuit (ASIC) design for artificial intelligence (AI) edge computing, especially the convolutional neural network (CNN) algorithm. However, SC has little to no optimization on field-programmable gate array (FPGA). Scaling up the ASIC logic without FPGA-oriented designs is inefficient, while aggregating thousands of bitstreams is still challenging in the conventional SC. This research has reinvented several FPGA-efficient 8-bit SC CNN computing architectures, i.e., SC multiplexer multiply-accumulate, multiply-accumulate function generator, and binary rectified linear unit, and successfully scaled and implemented a fully parallel CNN model on Kintex7 FPGA. The proposed SC hardware only compromises 0.14% accuracy compared to binary computing on the handwriting Modified National Institute of Standards and Technology classification task and achieved at least 99.72% energy saving per image feedforward and 31× more data throughput than modern hardware. Unique to SC, early decision termination pushed the performance baseline exponentially with minimum accuracy loss, making SC CNN extremely lucrative for AI edge computing but limited to classification tasks. The SC's inherent noise heavily penalizes CNN regression performance, rendering SC unsuitable for regression tasks.

A Wirelessly Powered Scattered Neural Recording Wearable System.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 μW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12×12×5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 μVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.

Design and development of MEMS quartz gyroscope measurement and control circuit with automatic gain control principle

Angular velocity is a very important measurement parameter for autonomous driving and industrial applications. The design of MEMS quartz gyro measurement and control circuit has always been the key to restricting the measurement angular velocity performance of gyro system. This paper introduces the application-specific integrated circuit (ASIC) design and implementation of a MEMS quartz gyro measurement and control circuit for angular velocity measurement. The designed nonlinear multiplier can use a square wave to drive the gyro’s sensitive structure at the beginning of gyro start-up, thereby reducing the gyro power-up time. The drive circuit replaces the PLL with an automatic gain control unit composed of peak detection and proportional integration (PI) controller, which makes the MEMS gyro system have good robustness. First, SIMULINK is used to model and simulate the MEMS gyroscope system-level model, which illustrates the feasibility of the drive circuit design scheme. Then, the operating principle of the drive loop is analyzed, and the design of the key circuit modules of the measurement and control circuit is introduced. Finally, the performance of the gyroscope drive and detection circuit is experimentally tested, the amplitude and frequency uncertainty of the gyroscope drive circuit are evaluated, and the bias instability and nonlinearity of the gyroscope are tested, the experiment results show that the gyroscope has good performance.

Versatile On-Chip Programming of Circuit Hardware for Wearable and Implantable Biomedical Microdevices.

Wearable and implantable microscale electronic sensors have been developed for a range of biomedical applications. The sensors, typically millimeter size silicon microchips, are sought for multiple sensing functions but are severely constrained by size and power. To address these challenges, a hardware programmable application-specific integrated circuit design is proposed and post-process methodology is exemplified by the design of battery-less wireless microchips. Specifically, both mixed-signal and radio frequency circuits are designed by incorporating metal fuses and anti-fuses on the top metal layer to enable programmability of any number of features in hardware of the system-on-chip (SoC) designs. This is accomplished in post-foundry editing by combining laser ablation and focused ion beam processing. The programmability provided by the technique can significantly accelerate the SoC chip development process by enabling the exploration of multiple internal circuit parameters without the requirement of additional programming pads or extra power consumption. As examples, experimental results are described for sub-millimeter size complementary metal-oxide-semiconductor microchips being developed for wireless electroencephalogram sensors and as implantable microstimulators for neural interfaces. The editing technique can be broadly applicable for miniaturized biomedical wearables and implants, opening up new possibilities for their expedited development and adoption in the field of smart healthcare.

A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists

Field Programmable Gate Arrays (FPGAs) provide a flexible compute platform for quick prototyping or hardware acceleration in diverse application domains. However, similar to the global semiconductor life-cycle in the modern supply chain, FPGA-based product development includes processes and interactions with potentially untrusted parties outside the traditional scrutiny of a completely in-house development cycle. An untrusted party or software can maliciously alter a hardware intellectual property (IP) block mapped to an FPGA device during various stages of the FPGA life-cycle. Such malicious alterations, also known as hardware Trojan attacks, have garnered significant research into their detection and prevention in the context of application-specific integrated circuit (ASIC) design flow. However, Trojan attacks in FPGAs have not enjoyed this same attention. Designers often rely on mapping ASIC-specific solutions and evaluation benchmarks to the FPGA domain, which leaves much of the FPGA-specific Trojan space uncovered. We note that the distinctive business model as well as the architectural configurations of FPGAs present unique opportunities for Trojan attacks to an adversary. To this end, we introduce a framework to automatically explore the hardware Trojan attack space in FPGA netlists. It is capable of inserting different types of FPGA-specific Trojans in a netlist enabling rapid exploration of potential Trojan attacks in an FPGA design: soft-template, monolithic, and distributed dark silicon. Soft template Trojans use behavioral templates with random synthesis constraints to increase Trojan structural diversity. Monolithic and distributed dark silicon Trojans use the under-utilized input space (FPGA dark silicon) in FPGA primitives to realize Trojans with effectively zero area and power footprint. Further optimizations are also presented to remove any potential delay impact. We then generate over 1300 Trojan-inserted benchmarks using each of the introduced FPGA Trojan classes, and compare their impact on utilization, delay, and power. Finally, we evaluate our Trojans against a machine learning-based Trojan detection to highlight their evasiveness.

Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks

In this article, the modified Pietra-Ricci index detector (mPRIDe) is devised, and its field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs are reported. The mPRIDe attains lower implementation complexity with respect to its predecessor, without performance penalty. Moreover, the mPRIDe is blind, robust against time-varying noise and received signal powers, and exhibits the constant false alarm rate property. Two versions of the mPRIDe, namely mPRIDe v1 and mPRIDe v2, have been designed. The former privileges lower hardware complexity, whereas the latter aims lower latency, with both versions having a linear scalability with the number of sensors in cooperation. In comparison with the smallest area consumed by a state-of-the-art sensor, mPRIDe v1 and mPRIDe v2 consume 56.6% and 47.3% lower areas, respectively. The sensing times of the proposed sensors are 1.6 and 2.9 times better than the fastest sensing time of contemporary sensors. Moreover, the proposed designs deliver the lowest area-time-product and power-delay-product among state-of-the-art implementations. These metrics make both mPRIDe v1 and mPRIDe v2 the most hardware-efficient and power-efficient sensors reported in the literature.

Design of MEMS gyroscope interface ASIC with on-chip temperature compensation

Zero bias and scale factor are important overall performance indicators for micromechanical gyroscopes and are commonly used to describe the temperature stability of MEMS gyroscope. This article presents a mode-matched MEMS gyroscope interface Application Specific Integrated Circuit (ASIC) with on-chip temperature compensation, which improves the temperature adaptability of the gyroscope by means of temperature compensation. By establishing a mathematical model between the equivalent integration constant of the driving loop and the temperature, the relationship between the phase margin of driving loop and temperature is analyzed. The effect of sense loop control parameters on the bandwidth of the gyroscope system is investigated, and the influence law between bandwidth and loop gain of the sense circuit is verified. A temperature compensation method based on an on-chip virtual temperature sensor is presented, and the design principle with an on-chip temperature compensation interface ASIC is described. The experimental results show that the standard deviation of scale factor in the temperature range of −40 to 60 °C is reduced to 11.2% of that before compensation, and the standard deviation of the zero bias is reduced to 2.5%. The zero bias instability of the gyroscope is reduced from 4.6 to 1.9°/h of that before compensation.

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

SummaryIntegrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error‐prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy‐based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High‐level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi‐objective optimization problem of finding a set of Pareto‐optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)‐based HLS methods for multi‐Vcc application‐specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)‐based and integer linear programming (ILP)‐based methods and showed their effectiveness in finding optimum or near‐optimum results in a short running time. SA‐based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA‐based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow

Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.

An Interface ASIC Design of MEMS Gyroscope with Analog Closed Loop Driving.

This paper introduces a digital interface application-specific integrated circuit (ASIC) for a micro-electromechanical systems (MEMS) vibratory gyroscope. The driving circuit of the interface ASIC uses an automatic gain circuit (AGC) module instead of a phase-locked loop to realize a self-excited vibration, which gives the gyroscope system good robustness. In order to realize the co-simulation of the mechanically sensitive structure and interface circuit of the gyroscope, the equivalent electrical model analysis and modeling of the mechanically sensitive structure of the gyro are carried out by Verilog-A. According to the design scheme of the MEMS gyroscope interface circuit, a system-level simulation model including mechanically sensitive structure and measurement and control circuit is established by SIMULINK. A digital-to-analog converter (ADC) is designed for the digital processing and temperature compensation of the angular velocity in the MEMS gyroscope digital circuit system. Using the positive and negative diode temperature characteristics, the function of the on-chip temperature sensor is realized, and the temperature compensation and zero bias correction are carried out simultaneously. The MEMS interface ASIC is designed using a standard 0.18 μM CMOS BCD process. The experimental results show that the signal-to-noise ratio (SNR) of sigma-delta (ΣΔ) ADC is 111.56 dB. The nonlinearity of the MEMS gyroscope system is 0.03% over the full-scale range.

Neurostimulators for high-resolution artificial retina: ASIC design challenges and solutions

Objective. Neurostimulator is one of the most important part in artificial retina design. In this paper, we discuss the main challenges in the design of application-specific integrated circuit for high-resolution artificial retina and suggest corresponding solutions. Approach. Problems in the design of the neurostimulator for the existing artificial retina have not been solved yet are analyzed and solutions are presented. For verification of the solutions, mathematical proof, MATLAB and Ansys simulations are used. Main results. The drawbacks of resorting to a high-voltage complementary metal oxide semiconductor (CMOS) process to deal with the large voltage compliance demanded by the stimulator output stage are pointed out, and an alternative approach based on a circuit that switches the voltage of the common reference electrode is proposed to overcome. The necessity of an active discharge circuit to remove the residual charge of electrodes caused by an unbalanced stimulus is investigated. We present a circuit analysis showing that the use of a passive discharge circuit is sufficient to suppress problematic direct current in most situations. Finally, possible restrictions on input and output (I/O) count are investigated by estimating the resistive-capacitive delay caused by the interconnection between the I/O pad and the microelectrode array. Significance. The results of this paper clarified the problems currently faced by neurostimulator design for the artificial retina. Through the solutions presented in this study, circuits with more competitiveness in power and area consumption can be designed.

Neuromorphic Functional Modules of a Spiking Neural Network

In the current era, the design and development of artificial neural networks exploiting the architecture of the human brain have evolved rapidly. Artificial neural networks (ANN) effectively solve a wide range of common artificial-intelligence tasks involving data classification and recognition, prediction, forecasting and adaptive control of the behavior of an object. The biologically inspired underlying principles of ANN operation have certain advantages over the conventional von Neumann architecture including unsupervised learning, architectural flexibility and adaptability to environmental change and high performance under significantly reduced power consumption due to large parallel and asynchronous data processing. In this paper, we present a circuit design of main functional blocks (neurons and synapses) intended for the hardware implementation of a perceptron-based feedforward spiking neural network. As the third generation of artificial neural networks, spiking neural networks perform data processing utilizing spikes, which are discrete events (or functions) that take place at points in time. Neurons in spiking neural networks initiate precisely timed spikes and communicate with each other via spikes transmitted through synaptic connections or synapses with adaptable scalable weight. One of the prospective approaches to emulating synaptic behavior in hardware implemented spiking neural networks is to use nonvolatile-memory devices with analog conduction modulation (or memristive structures). Here we propose a circuit design for functional analogues of memristive structures to mimic synaptic plasticity, pre- and postsynaptic neurons which could be used for developing a circuit design of spiking-neural-network architectures with different training algorithms including the spike-timing-dependent-plasticity learning rule. Two different circuits of an electrical synapse are developed. The first one is an analog synapse with a photoresistor optocoupler used to ensure the tunable conductivity for synaptic-plasticity emulation. While the second one is a digital synapse, in which the synaptic weight is stored in a digital code with its direct conversion into conductivity (without a digital-to-analog converter and photoresistor optocoupler). The results of prototyping the developed circuits for electronic analogs of synapses, pre- and postsynaptic neurons and the study of transient processes are presented. The developed approach could provide a basis for the ASIC (application-specific integrated circuit) design of spiking neural networks based on CMOS (complementary metal—oxide–semiconductor) design technology.

A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers

Neural network pruning, which can be divided into unstructured pruning and structured pruning strategies, has been proven to be an efficient method to substantially reduce the number of computations of convolutional neural networks (CNNs). However, it remains difficult to combine the advantages of these two pruning strategies. This article proposes a high-performance accelerator for unstructured sparse CNNs. First, a convolution-based filter selection and clustering method (FSCM) is proposed to reorder unstructured sparse filters into uniform-size dense filters, eliminating redundant computations in the convolutional layers while maintaining a regular structure. In addition, a convolution and pooling calculation method (CPCM) is presented to reduce interlayers’ computational redundancy. Third, a hardware accelerator with high digital signal processing (DSP) efficiency is designed to take advantage of FSCM and CPCM. The proposed accelerator is implemented on a Xilinx XCVU9P platform at 300 MHz. With different CNN configurations, the performance and DSP efficiency for LeNet, AlexNet, and VGG16 are 1490.53 GOPS and 3.882, 913.85 GOPS and 1.785, and 862.16 GOPS and 1.68, respectively. Compared to previous field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, the accelerator achieves up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15.43\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.73\times $ </tex-math></inline-formula> speedup in terms of performance and DSP efficiency.

A Waveform Sampling Prototype ASIC for Picosecond-Level Time Measurement

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction.

A Neuromorphic Processing System With Spike-Driven SNN Processor for Wearable ECG Classification.

This paper presents a neuromorphic processing system with a spike-driven spiking neural network (SNN) processor design for always-on wearable electrocardiogram (ECG) classification. In the proposed system, the ECG signal is captured by level crossing (LC) sampling, achieving native temporal coding with single-bit data representation, which is directly fed into an SNN in an event-driven manner. A hardware-aware spatio-temporal backpropagation (STBP) is suggested as the training scheme to adapt to the LC-based data representation and to generate lightweight SNN models. Such a training scheme diminishes the firing rate of the network with little plenty of classification accuracy loss, thus reducing the switching activity of the circuits for low-power operation. A specialized SNN processor is designed with the spike-driven processing flow and hierarchical memory access scheme. Validated with field programmable gate arrays (FPGA) and evaluated in 40 nm CMOS technology for application-specific integrated circuit (ASIC) design, the SNN processor can achieve 98.22% classification accuracy on the MIT-BIH database for 5-category classification, with an energy efficiency of 0.75 μJ/classification.

Design, integration and implementation of crypto cores in an SoC environment

PurposeThe paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Pulsed-Laser Testing to Quantitatively Evaluate Latchup Sensitivity in Mixed-Signal ASICs

Pulsed-laser testing is used to accurately determine single-event latchup (SEL) thresholds for static random-access memories (SRAMs) with different body-tie-to-drain spacings on a mixed-signal application-specific integrated circuit (ASIC), a study that could not be completed using only broad-beam heavy-ion testing. Two distinct approaches were employed with the first approach, an empirical correlation method, exploiting the complementary nature of broad-beam heavy-ion and laser testing. Various single- and dual-port SRAMs exhibited SEL thresholds ranging from 1 MeV-cm²/mg to over 100 MeV-cm²/mg, with a dual-port device possessing the smallest body-tie-to-drain spacing being latchup immune at the highest available test conditions (&#x003E;300 MeV-cm²/mg). These results have been used to inform a follow-on ASIC design resulting in a significant improvement in chip-level SEL sensitivity. The second approach, a calculational method, uses pulsed-laser measurements and charge-deposition modeling to predict linear energy transfer (LET) thresholds without heavy-ion data. This calculational approach agrees with the empirical approach and therefore shows promise as a predictive tool for SEL threshold estimation, but further validation is required. Overall, these approaches can be effective tools for evaluating SEL susceptibilities and mitigation strategies.