Application Specific Integrated Chip Research Articles

PIM GPT a hybrid process in memory accelerator for autoregressive transformers

Decoder-only Transformer models such as Generative Pre-trained Transformers (GPT) have demonstrated exceptional performance in text generation by autoregressively predicting the next token. However, the efficiency of running GPT on current hardware systems is bounded by low compute-to-memory-ratio and high memory access. In this work, we propose a Process-in-memory (PIM) GPT accelerator, PIM-GPT, which achieves end-to-end acceleration of GPT inference with high performance and high energy efficiency. PIM-GPT leverages DRAM-based PIM designs for executing multiply-accumulate (MAC) operations directly in the DRAM chips, eliminating the need to move matrix data off-chip. Non-linear functions and data communication are supported by an application specific integrated chip (ASIC). At the software level, mapping schemes are designed to maximize data locality and computation parallelism. Overall, PIM-GPT achieves 41 − 137 × , 631 − 1074 × speedup and 123 − 383 × , 320 − 602 × energy efficiency over GPU and CPU baseline on 8 GPT models with up to 1.4 billion parameters.

Generic and Cost effective framework for Space Threat Assessment for Emerging Space Economies

Modern-day satellites can be considered mini-computers orbiting the earth, with their own operating systems, customized software, navigation and processing units, in-built memory, and other optical and communication capabilities. Gone are the days when satellites were huge in size, with systems and sub-systems taking several months to a few years to be manufactured, assembled, tested, and launched depending on the mission. A wide variety of technological developments in the past decades, including miniaturization of systems and subsystems, availability of space-qualified and commercially-off-the-shelf (COTS) components, and the advent of application-specific integrated chips (ASICs) have paved the way for an increase in quantity and quality of space-based systems, thereby enabling a wide variety of missions even for emerging space economies. With the growing number and complexity of satellites, there have been multiple recorded instances of attacks that have happened on space and ground-based systems over the last three decades. For example, in 1986, the Galaxy I satellite uplink was disrupted by a suspicious person from Florida under the pseudonym "Captain Midnight". In 1997, computers belonging to the X-ray astrophysics section of the Goddard Space Flight Center campus were compromised. In 1998, the ROSAT X-RAY satellite co-owned by the United States and Germany was hacked. One of the satellites from the military communication system Skynet - owned and operated by the UK's Royal Air Force was hacked. As we enter the space age, it is important to note that many countries, including underdeveloped nations, utilize satellites for various earth-based and space-based applications, military recon missions, interplanetary missions, and all other types of space exploration. Given the extent of utilization, it is crucial to tackle the threats facing space-based and ground-based systems. Some developed and space-faring nations like the USA, Russia, China, the UK, etc., have counter-space capabilities at present to tackle a wide variety of threats. On the other hand, countries like India, Iran, Australia, New Zealand, and UAE, which are still new or emerging players in the new space industry, are still developing their systems to be robust enough to tackle space-based and ground-based threats. At the farther end are countries like Mongolia, Nepal, Sri Lanka, Cambodia, Norway, etc., which are still developing their space capabilities. In this concise abstract, we present an overview of the myriad security threats encountered by both space-based and ground-based systems. Additionally, we introduce a generic and cost-effective threat assessment framework designed to evaluate these threats across diverse scenarios. This mission-agnostic framework, along with its brief methodology, serves as a foundational tool for identifying security vulnerabilities and formulating comprehensive risk mitigation strategies tailored to specific missions. In the subsequent full-length article, we delve deeper into the complexities of space security, exploring real-world examples, emerging challenges, and innovative solutions.

An alternative test method for the dual-port SRAM through the DesignWare SATA AHCI implementation in 3D IC structures

The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14 nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.

Ambient Light Rejection Integrated Circuit for Autonomous Adaptation on a Sub-Retinal Prosthetic System.

This paper introduces an ambient light rejection (ALR) circuit for the autonomous adaptation of a subretinal implant system. The sub-retinal implants, located beneath a bipolar cell layer, are known to have a significant advantage in spatial resolution by integrating more than a thousand pixels, compared to epi-retinal implants. However, challenges remain regarding current dispersion in high-density retinal implants, and ambient light induces pixel saturation. Thus, the technical issues of ambient light associated with a conventional image processing technique, which lead to high power consumption and area occupation, are still unresolved. Thus, it is necessary to develop a novel image-processing unit to handle ambient light, considering constraints related to power and area. In this paper, we present an ALR circuit as an image-processing unit for sub-retinal implants. We first introduced an ALR algorithm to reduce the ambient light in conventional retinal implants; next, we implemented the ALR algorithm as an application-specific integrated chip (ASIC). The ALR circuit was fabricated using a standard 0.35-μm CMOS process along with an image-sensor-based stimulator, a sensor pixel, and digital blocks. As experimental results, the ALR circuit occupies an area of 190 µm2, consumes a power of 3.2 mW and shows a maximum response time of 1.6 s at a light intensity of 20,000 lux. The proposed ALR circuit also has a pixel loss rate of 0.3%. The experimental results show that the ALR circuit leads to a sensor pixel (SP) being autonomously adjusted, depending on the light intensity.

CATIROC: an integrated chip for neutrino experiments using photomultiplier tubes

An ASIC (Application Specific Integrated Chip) named CATIROC (Charge And Time Integrated Read Out Chip) has been developed for the next-generation neutrino experiments using a large number of photomultiplier tubes (PMTs). Each CATIROC provides the time and the charge measurements for 16 configurable input channels operating in auto-trigger mode. Originally designed for the light emission in water Cherenkov detectors, we show in this paper that its use can be extended to liquid-scintillator based experiments. The ∼ 26000 3-inch PMTs of the JUNO experiment, under construction in China, is a case in point. This paper describes the features of CATIROC with a special attention to the most critical points for its application to the time profile of the light emission in liquid scintillators. The achieved performances in both charge and time measurements can be inputs for future high-precision experiments making use of PMTs or other photo-sensitive detectors.

Area Efficient Parallel Median Filter Using Approximate Comparator and Faithful Adder

Approximate computing is a novel approach to design area-efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre-sorter and post-merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing window. Approximate compare and swap (CS) blocks that can trade off area at the expense of accuracy are proposed and used in the proposed PMF. Two variants of PMF are realised based on the implementation of approximate CS units in the pre-sorter and post-merge blocks. In PMF-design1, the authors use the exact CS unit in the pre-sorter and approximate CS unit in the post-merge block (hereafter referred to as P-EA) and in PMF-design2, they use approximate CS unit in both pre-sorter and post-merge blocks (hereafter referred to as P-AA). Functionality and accuracy efficacy of the proposed PMFs are verified with the image de-noising application. Synthesis with 90 nm application specific integrated chip technology revealed that to the least, proposed PMFs demonstrate 33.75 and 41.9% area-delay product and power-delay product reductions, respectively, compared to the standard median filter.

Design and Research of under-Voltage Protection Circuit for Motor Driver Chip Based on Special Integrated Chip

Intelligent power integrated circuit chips play an increasingly important role in industrial automation, domestic medical appliances, automotive electronics, especially in modern military, aerospace and other fields. Based on the analysis of the current front-end verification problem of digital application specific integrated chip, the composition and working principle of motor drive chip, the design and composition technology of undervoltage protection function module and the perfect protection circuit not only ensure that the chip can work normally under some harsh conditions, but also play a vital role in the safety of the whole system sometimes. After the motor chip is verified by the flow sheet, packaging, testing and test result analysis are carried out to further predict and adjust the function and reliability of the motor chip. On the basis of analyzing the current front-end verification problem of digital application specific integrated chip, the circuit structure is simple, no additional bandgap reference circuit is needed, and the voltage comparator circuit is also omitted.

A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring.

This paper presents the first application specific integrated chip (ASIC) for the monitoring of patients who have suffered a Traumatic Brain Injury (TBI). By monitoring the neurophysiological (ECoG) and neurochemical (glucose, lactate and potassium) signals of the injured human brain tissue, it is possible to detect spreading depolarisations, which have been shown to be associated with poor TBI patient outcome. This paper describes the testing of a new 7.5 mm2 ASIC fabricated in the commercially available AMS 0.35 μm CMOS technology. The ASIC has been designed to meet the demands of processing the injured brain tissue's ECoG signals, recorded by means of depth or brain surface electrodes, and neurochemical signals, recorded using microdialysis coupled to microfluidics‐based electrochemical biosensors. The potentiostats use switchedcapacitor charge integration to record currents with 100 fA resolution, and allow automatic gain changing to track the falling sensitivity of a biosensor. This work supports the idea of a “behind the ear” wireless microplatform modality, which could enable the monitoring of currently non‐monitored mobile TBI patients for the onset of secondary brain injury.

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications

Memory‐efficient SURF architecture for ASIC implementation

Among the image features for object recognition, speeded up robust features (SURF) have been widely implemented due to their hardware-friendly characteristics and high accuracy. However, because of adopting a fully internal memory-based architecture and a field programmable gate array having large memories for a high performance, most of them are infeasible to the application specific integrated chip (ASIC). A memory-efficient architecture for implementing SURF in ASIC by analysing the characteristics of memory accesses of SURF is presented. In addition, a strategy of dividing an entire image into multiple sub-images, processing them sequentially and overlapping each other to reduce the size of the internal memory while minimising the loss of information is proposed. The proposed architecture was implemented with 767 kb-sized internal memories and 1.2 M logic gates while processing 60 frames per second.

Design and Development of Two Axis Control and Drive for PMSM Motor of In-Service Inspection Module for PFBR Steam Generator

Abstract The accuracy of the servo system is dependent on the speed or band width of the closed loop control system. To achieve the high speed closed loop operation, hardware oriented control is preferred and it is achieved by means of an ASIC (Application Specific Integrated Chip). The servo system is used to drive a two axis robotic arm moving in a plane where two PMSM motor with servo control provides the required motion. Robotic applications require quick and accurate changes in driving torque so that the required motion behaviour is attained. Quick change in operating flux is required for fast and accurate servo control. Conventional scalar control drives cannot achieve quick response time and hence vector control is employed. The IRMCK201 ASIC used in the application has the Vector Control algorithm hard wired into it for complete servo control of a single PMSM. It takes the position and current feed back by using shaft encoder, hall sensor and IR2175 Current sensing IC. It can set up communication with a host controller through either high speed serial, SPI or Parallel protocols. The inverter unit is implemented using an Intelligent Power Module (IPM) and it is driven by the Space Vector Modulation signals from IRMCK201. The work shows that highly efficient servo drive can be implemented using IRMCK201 and Host controller with PMSM.

Convergence and stability analysis of a digital automatic gain control

SUMMARYThis paper is dedicated to the theoretical analysis of a digital automatic gain control (AGC), which feedbacks according to the desired output direct current (DC). First, we mathematically model the AGC, with the input signal interfered by AWGN. As it turns out, the loop model is a first‐order varying‐coefficient stochastic difference equation, and its solution consists of two parts, that is, the transient state and the steady state, which respectively explain the convergence and stability of the AGC. As is shown in the paper, the properties of convergence and stability of AGC are mutually contradictory, and both are determined by a key parameter in the loop, and the parameter is defined as the feedback sensitivity of the loop. The results of the paper are validated by numerical simulation, and they are of theoretical guide for practical digital AGC implementation on Application Specific Integrated Chips (ASICs) or Field Programmable Gate Arrays (FPGAs). Copyright © 2013 John Wiley & Sons, Ltd.

Development of a prototype of the ME readout electronics onboard the HXMT satellite

A prototype of the ME readout electronics onboard the Hard X-ray Modulate Telescope (HXMT) satellite is developed. Application Specific Integrated Chip (ASIC) is used to construct the front end electronics due to a large number of detectors. Field Programmable Gate Array (FPGA) is connected to the ASIC as a state machine controller and data FIFO in the DAQ system. A USB board is designed to communicate between the DAQ system and the computer. The design goals and features, the operation of the system and the preliminary performance of the prototype are described. The testing results show that the design goals of the prototype system have been achieved.

MEMS-based 3D accelerometers for land seismic acquisition: Is it time?

Recent advances have allowed development of micro electro mechanical system (MEMS) sensors with the sensitivity, low noise, and dynamic range needed in seismic acquisition. This is a possible “breakthrough” because MEMS accelerometers have the potential to provide broader bandwidth, more accurate amplitude, and less sensitivity to planting tilt than the coil-based geophones that have long been used in the industry. Several papers have presented the advantages of three-component acquisition with single digital sensors based on MEMS, and the advent of these sensors has been promoted as the next big advance in land seismic acquisition—much like the shift to 24-bits recording systems 10 years ago. So, this is a good time to ask an obvious question: Has this technology really advanced to the point that it can, or should, be used for general-purpose land seismic acquisition? This paper will attempt to answer that question by addressing the advantages and disadvantages for the general application of single 3C digital sensors. Ground motion can be measured as displacement, velocity, or acceleration. A mass/spring assembly is used for all these measurements. With a soft spring, the mass (the coil in the geophone) does not move and represents the reference for displacement or velocity measurements. With a stiff spring, the mass moves with the case, but with a small residual displacement related to the acceleration. This acceleration can be measured either by the strain on the spring (e.g., low cost, low power, high distortion air bags) or by a feedback force applied to the mass to cancel the displacement (e.g., high performance digital sensors requiring power supply). In this last implementation the sensor based on MEMS is still analog, while the control loop and the output provided by an application specific integrated chip (ASIC) are digital. Such a “digital” sensor is much smaller than the …