Memory‐efficient SURF architecture for ASIC implementation

Abstract

Among the image features for object recognition, speeded up robust features (SURF) have been widely implemented due to their hardware-friendly characteristics and high accuracy. However, because of adopting a fully internal memory-based architecture and a field programmable gate array having large memories for a high performance, most of them are infeasible to the application specific integrated chip (ASIC). A memory-efficient architecture for implementing SURF in ASIC by analysing the characteristics of memory accesses of SURF is presented. In addition, a strategy of dividing an entire image into multiple sub-images, processing them sequentially and overlapping each other to reduce the size of the internal memory while minimising the loss of information is proposed. The proposed architecture was implemented with 767 kb-sized internal memories and 1.2 M logic gates while processing 60 frames per second.