Application Runtime Research Articles

Asynchronous adaptive optimisation for generic data‐parallel array programming

SUMMARYProgramming productivity very much depends on the availability of basic building blocks that can be reused for a wide range of application scenarios and the ability to define rich abstraction hierarchies. Driven by the aim for increased reuse, such basic building blocks tend to become more and more generic in their specification; structural as well as behavioural properties are turned into parameters that are passed on to lower layers of abstraction where eventually a differentiation is being made. In the context of array programming, such properties are typically array ranks (number of axes/dimensions) and array shapes (number of elements along each axis/dimension). This allows for abstract definitions of operations such as element‐wise additions, concatenations, rotations, and so on, which jointly enable a very high‐level compositional style of programming, similar to, for instance, MATLAB. However, such a generic programming style generally comes at a price in terms of runtime overheads when compared against tailor‐made low‐level implementations. Additional layers of abstraction as well as the lack of hard‐coded structural properties often inhibits optimisations that are obvious otherwise. Although complex static compiler analyses and transformations such as partial evaluations can ameliorate the situation to quite some extent, there are cases, where the required level of information is not available until runtime. In this paper, we propose to shift part of the optimisation process into the runtime of applications. Triggered by some runtime observation, the compiler asynchronously applies partial evaluation techniques to frequently used program parts and dynamically replaces initial program fragments by more specialised ones through dynamic re‐linking. In contrast to many existing approaches, we suggest this optimisation to be done in a rather non‐intrusive, decoupled way. We use a full‐fledged compiler that is run on a separate core. This measure enables us to run the compiler on its highest optimisation‐level, which requires non‐negligible compilation times for our optimisations. We use the compiler's type system to identify the potential dynamic optimisations. And we use the host language's module system as a facilitator for the dynamic code modifications. We present the architecture and implementation of an adaptive compilation framework for Single Assignment C, a data‐parallel array programming language. Single Assignment C advocates shape‐generic and rank‐generic programming with arrays. A sophisticated, highly optimising compiler technology nevertheless achieves competitive runtime performance. We demonstrate the suitability of our approach to achieve consistently high performance independent of the static availability of array properties by means of several experiments based on a highly generic formulation of rank‐invariant convolution as a case study. Copyright © 2011 John Wiley & Sons, Ltd.

A context realization framework for ubiquitous applications with runtime support

Context awareness, as one of the key techniques applied in ubiquitous computing, makes information technology invisible and seamless to people's daily living. As a result, numerous context frameworks have been developed for simplifying the development of context-aware applications by providing low-level context data operations such as acquisitions and simple aggregations in terms of APIs or toolkits. These frameworks are still falling short in requiring developers to explicitly deal with context-related tasks such as constraint enforcement in the application code. In this article, we present a framework to bridge the gap. More specifically, an application context model (ACM) is proposed for developers to specify their requirements on the context-related tasks. At application runtime, the ACM is instantiated for automatic context realization by the application context engine (ACE), which supports the full life cycle of each ACM instance (initialization, execution, and termination). We validate the concept of the framework through a case study, and present the experimental results based on the system prototype.

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as those based on directory caches. However, the limited directory cache size of the increasingly larger systems may cause frequent evictions of directory entries and, consequently, invalidations of cached blocks, which severely degrades system performance. A significant percentage of the referred memory blocks are only accessed by one processor (even in parallel applications) and, therefore, do not require coherence maintenance. Taking advantage of techniques that dynamically identify those private blocks, we propose to deactivate the coherence protocol for them and to treat them as uniprocessor systems do. The protocol deactivation allows directory caches to omit the tracking of an appreciable quantity of blocks, which reduces their load and increases their effective size. Since the operating system collaborates on the detection of private blocks, our proposal only requires minor modifications. Simulation results show that, thanks to our proposal, directory caches can avoid the tracking of about 57% of the accessed blocks and their capacity can be better exploited. This contributes either to shorten the runtime of parallel applications by 15% while keeping directory cache size or to maintain system performance while using directory caches 8 times smaller.

A comparative study of GPU programming models and architectures using neural networks

Recently, General Purpose Graphical Processing Units (GP-GPUs) have been identified as an intriguing technology to accelerate numerous data-parallel algorithms. Several GPU architectures and programming models are beginning to emerge and establish their niche in the High-Performance Computing (HPC) community. New massively parallel architectures such as the Nvidia’s Fermi and AMD/ATi’s Radeon pack tremendous computing power in their large number of multiprocessors. Their performance is unleashed using one of the two GP-GPU programming models: Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL). Both of them offer constructs and features that have direct bearing on the application runtime performance. In this paper, we compare the two GP-GPU architectures and the two programming models using a two-level character recognition network. The two-level network is developed using four different Spiking Neural Network (SNN) models, each with different ratios of computation-to-communication requirements. To compare the architectures, we have chosen the two extremes of the SNN models for implementation of the aforementioned two-level network. An architectural performance comparison of the SNN application running on Nvidia’s Fermi and AMD/ATi’s Radeon is done using the OpenCL programming model exhausting all of the optimization strategies plausible for the two architectures. To compare the programming models, we implement the two-level network on Nvidia’s Tesla C2050 based on the Fermi architecture. We present a hierarchy of implementations, where we successively add optimization techniques associated with the two programming models. We then compare the two programming models at these different levels of implementation and also present the effect of the network size (problem size) on the performance. We report significant application speed-up, as high as 1095× for the most computation intensive SNN neuron model, against a serial implementation on the Intel Core 2 Quad host. A comprehensive study presented in this paper establishes connections between programming models, architectures and applications.

TRAM (Transcriptome Mapper): database-driven creation and analysis of transcriptome maps from multiple sources

BackgroundSeveral tools have been developed to perform global gene expression profile data analysis, to search for specific chromosomal regions whose features meet defined criteria as well as to study neighbouring gene expression. However, most of these tools are tailored for a specific use in a particular context (e.g. they are species-specific, or limited to a particular data format) and they typically accept only gene lists as input.ResultsTRAM (Transcriptome Mapper) is a new general tool that allows the simple generation and analysis of quantitative transcriptome maps, starting from any source listing gene expression values for a given gene set (e.g. expression microarrays), implemented as a relational database. It includes a parser able to assign univocal and updated gene symbols to gene identifiers from different data sources. Moreover, TRAM is able to perform intra-sample and inter-sample data normalization, including an original variant of quantile normalization (scaled quantile), useful to normalize data from platforms with highly different numbers of investigated genes. When in 'Map' mode, the software generates a quantitative representation of the transcriptome of a sample (or of a pool of samples) and identifies if segments of defined lengths are over/under-expressed compared to the desired threshold. When in 'Cluster' mode, the software searches for a set of over/under-expressed consecutive genes. Statistical significance for all results is calculated with respect to genes localized on the same chromosome or to all genome genes. Transcriptome maps, showing differential expression between two sample groups, relative to two different biological conditions, may be easily generated. We present the results of a biological model test, based on a meta-analysis comparison between a sample pool of human CD34+ hematopoietic progenitor cells and a sample pool of megakaryocytic cells. Biologically relevant chromosomal segments and gene clusters with differential expression during the differentiation toward megakaryocyte were identified.ConclusionsTRAM is designed to create, and statistically analyze, quantitative transcriptome maps, based on gene expression data from multiple sources. The release includes FileMaker Pro database management runtime application and it is freely available at http://apollo11.isto.unibo.it/software/, along with preconfigured implementations for mapping of human, mouse and zebrafish transcriptomes.

On/off-line prediction applied to job scheduling on non-dedicated NOWs

This paper proposes a prediction engine designed for non-dedicated clusters, which is able to estimate the turnaround time for parallel applications, even in the presence of serial workload of the workstation owner. The prediction engine can be configured to work with three different estimation kernels: a Historical kernel, a Simulation kernel based on analytical models and an integration of both, named Hybrid kernel. These estimation proposals were integrated into a scheduling system, named CISNE, which can be executed in an on-line or off-line mode. The accuracy of the proposed estimation methods was evaluated in relation to different job scheduling policies in a real and a simulated cluster environment. In both environments, we observed that the Hybrid system gives the best results because it combines the ability of a simulation engine to capture the dynamism of a non-dedicated environment together with the accuracy of the historical methods to estimate the application runtime considering the state of the resources.

A network performance sensitivity metric for parallel applications

Excessive run time variability of parallel application codes on commodity clusters is a significant challenge. To gain insight into this problem, our earlier work developed tools to emulate parallel applications (PACE) by simulating computation and using the cluster's interconnection network for communication, and further study parallel application run time sensitivity effects to controlled network performance degradation (PARSE). This work expands our previous efforts by presenting a metric derived from PARSE test results conducted on several widely used parallel benchmarks and application code fragments. The metric suggests that a parallel application's sensitivity to network performance variation can be quantified relative to its behaviour in optimal network performance conditions. Ideas on how this metric can be useful to parallel application development, cluster system performance management and system administration are also presented.

상태감시컴포넌트를 사용한 OPRoS 프레임워크의 고장감내 기법

The OPRoS (Open Platform for Robotic Services) framework is proposed as an application runtime environment for service robot systems. For the successful deployment of the OPRoS framework, fault tolerance support is crucial on top of its basic functionalities of lifecycle, thread and connection management. In the previous work [1] on OPRoS fault tolerance supports, we presented a framework-based fault tolerance architecture. In this paper, we extend the architecture with component-based fault tolerance techniques, which can provide more simplicity and efficiency than the pure framework-based approach. This argument is especially true for fault detection, since most faults and failure can be defined when the system cannot meet the requirement of the application functions. Specifically, the paper applies two widely-used fault detection techniques to the OPRoS framework: 'bridge component' and 'process model' component techniques for fault detection. The application details and performance of the proposed techniques are demonstrated by the same application scenario in [1]. The combination of component-based techniques with the framework-based architecture would improve the reliability of robot systems using the OPRoS framework.

Microarchitectural Online Testing for Failure Detection in Memory Order Buffers

Technology scaling leads to burn-in phase out and higher postsilicon test complexity, which increases in-the-field failure rate due to both latent defects and actual errors, respectively. As a consequence, current reliability qualification methods will likely be infeasible. Microarchitecture knowledge of application runtime behavior offers a possibility to have low-cost continuous online testing techniques detect hard errors in the field. Whereas data can be protected with redundancy (like parity or ECC), there is a lack of mechanism for control logic. This paper proposes a microarchitectural approach for validating that the memory order buffer logic works correctly. Our design relies on a small cache-like structure that keeps track of the last store to each cached address. Each load is checked to have obtained the data from the youngest older producing store. We present three different implementations of this idea, offering different trade-offs for error coverage, performance overhead, and design complexity.

Dynamic Partitioning of GATE Monte-Carlo Simulations on EGEE

The EGEE Grid offers the necessary infrastructure and resources for reducing the running time of particle tracking Monte-Carlo applications like GATE. However, efforts are required to achieve reliable and efficient execution and to provide execution frameworks to end-users. This paper presents results obtained with porting the GATE software on the EGEE Grid, our ultimate goal being to provide reliable, user-friendly and fast execution of GATE to radiation therapy researchers. To address these requirements, we propose a new parallelization scheme based on a dynamic partitioning and its implementation in two different frameworks using pilot jobs and workflows. Results show that pilot jobs bring strong improvement w.r.t. regular gLite submission, that the proposed dynamic partitioning algorithm further reduces execution time by a factor of two and that the genericity and user-friendliness offered by the workflow implementation do not introduce significant overhead.

Resource-Aware Performance Diagnostic Method for Web Applications

This paper proposes a resource-aware performance diagnostic method.For transactions in Web applications,the proposed method constructs performance profile chains based on the resource service time,which is stable for different workload characteristics.According to the anomaly of resource service time at application runtime,the proposed method provides an efficient solution to performance anomaly detection,location and diagnosis.Experimental results show that this method can effectively detect performance anomalies caused by different resource bottlenecks with changing workload characteristics.

A free software package for a human onlineconditioned suppression preparation

MartiansV2 is both a language syntax in which experiments can be written and an implementation of this syntax in a runtime application that, when fed a valid experiment text file, will execute the given experiment. It is based on the original Martians preparation, which has proven a valuable tool for assessing human online-conditioned suppression performance through research on a wide array of learning phenomena. This article can be read as a manual, both for using the Martians paradigm in general and for getting started with MartiansV2.

New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

VisualGrid: enabling runtime applications monitoring in grid environments

Scientific visualisation represents an important tool to help researchers in understanding huge and complex results produced in the research laboratories. The purpose of this article is to describe how scientific visualisation techniques can be used in a grid environment in order to allow users to monitor the evolution of their applications. The development of an innovative software infrastructure, called 'VisualGrid', is described highlighting as the use of such solution may be very useful, especially in the presence of applications characterised by a long term execution. Users can save time by detecting misbehaviours or inefficiencies in their systems before the job execution on the grid infrastructure is finished. Technical and practical problems encountered during the development of 'VisualGrid' are discussed and a performance evaluation of the developed prototype is presented.

Serializable isolation for snapshot databases

Many popular database management systems implement a multiversion concurrency control algorithm called snapshot isolation rather than providing full serializability based on locking. There are well-known anomalies permitted by snapshot isolation that can lead to violations of data consistency by interleaving transactions that would maintain consistency if run serially. Until now, the only way to prevent these anomalies was to modify the applications by introducing explicit locking or artificial update conflicts, following careful analysis of conflicts between all pairs of transactions. This article describes a modification to the concurrency control algorithm of a database management system that automatically detects and prevents snapshot isolation anomalies at runtime for arbitrary applications, thus providing serializable isolation. The new algorithm preserves the properties that make snapshot isolation attractive, including that readers do not block writers and vice versa. An implementation of the algorithm in a relational DBMS is described, along with a benchmark and performance study, showing that the throughput approaches that of snapshot isolation in most cases.

MASA Stream Architecture and Evaluating for a Fluid Computing Application

This paper presents MASA stream architecture which supporting 64b operation for scientific computing,and which characteristics are stress locality,parallelism,decoupling of memory operations.It matches the capabilities of modern semiconductor technology with computer-intensive parallel applications and allows for high performance of compiler optimized code.Given a fluid computing application as a case,the authors used a cycle-accurate hardware simulator to analyze the performance of the implementation and to measure application run-time.A comparison with the code,tuned for traditional general purpose processors,confirms the stream processor's potential to deliver high performance.

Fuzzy Logic Supported Consistency Management in DDVEs

In distributed virtual environments, where avatars permanently change their properties (e.g. their position) or perform modifications on shared objects, inconsistent states may occur due to message latency or concurrent updates. Here, the consistency often falls prey to high interactivity and responsiveness demands. To minimize the presence of inconsistent states or data, the Elastic Consistency model aims at providing an optimal trade-off between consistency and system responsiveness. In this paper we present a Fuzzy Logic driven approach for the computation of this trade-off on the basis of environmental characteristics at the application runtime. Furthermore, we evaluate the impacts of this parameter on consistency and system responsiveness by adjusting the behavior of a classic mutual exclusion algorithm. In this paper we show that an acceptable degree of consistency with respect to required system responsiveness can be efficiently achieved, even when addressing a large number of users.

Polymorphic On-Chip Networks

As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application or workload. We propose polymorphic on-chip networks to enable per-application network customization. This network can be configured prior to application runtime, to have the topology and buffering of arbitrary network designs. This paper proposes one such polymorphic network architecture. We demonstrate its modes of configurability, and evaluate the polymorphic network architecture design space, producing polymorphic fabrics that minimize the network area overhead. Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network designs.

Achieving efficiency, quality of service and robustness in multi-organizational Grids

Scalability, flexibility, quality of service provisioning, efficiency and robustness are the desired characteristics of most computing systems. Although the emerging Grid computing paradigm is scalable and flexible, achieving both efficiency and quality of service provisioning in Grids is a challenging task but is necessary for the wide adoption of Grids. Grid middleware should also be robust to uncertainties such as those in user-estimated runtimes of Grid applications. In this paper, we present a complete middleware framework for Grids that achieves user satisfaction by providing QoS guarantees for Grid applications, cost effectiveness by efficiently utilizing resources and robustness by intelligently handling uncertain runtimes of applications.

QoS-Aware service management for component-based distributed applications

Component-based software development has evolved from a tightly coupled style to a loosely coupled style in the recent few years. The paradigm shift will eventually allow heterogeneous systems to interoperate in open networks such as the Internet and will make software development more of a management task than a development task. Envisioning that future applications may comprise dynamically aggregated component services possibly distributed widely, we develop a Quality of Service (QoS)-aware service management framework in the middleware layer to make the component services infrastructure transparent to the applications. Specifically, we manage services not only as individuals, but more importantly as meaningful aggregated entities based on the logical compositional needs coming from the applications, by composing services properly according to QoS requirements at application setup time, and performing continuous maintenance at application runtime seamlessly. Our service management framework is scalable in two dimensions: network size and application's client population size. Specifically, the framework employs a decentralized management solution that scales to large network size, and explores resource sharing in one-to-many group-based applications by means of multicasting mechanisms. Moreover, it incorporates local adaptation operations and distributed failure detection, reporting, and recovery mechanisms to deal with runtime resource fluctuations and failures.