Low-voltage Applications Research Articles

A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications

A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-voltage and low-power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock transitions with footed differential latches and the same area as a conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at a low supply voltage regime, achieving wide-range voltage scalability (1–0.3 V). The measurement results with a test chip fabricated in 28-nm CMOS technology show that power consumption is reduced by 64%/56% with a 0%/10% activity ratio at 1 V compared to that of a TGFF. All 100 dies from five process corners were functional with supply voltage as low as 0.28 V.

A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications

An operational trans-conductance amplifier (OTA) is a fundamental component of electronic appliances. This paper introduces a novel design of OTA for minimal power, low voltage applications. The proposed OTA comprises an ultra low power current mirror design with enhanced bandwidth. The proposed OTA circuit is operated at 0.8[Formula: see text]V, contributing input noise of 26.33[Formula: see text]nV/(Hz)[Formula: see text] with a power of [Formula: see text]W. The additional parameters of new OTA are DC gain (87.32[Formula: see text]dB), common mode rejection ratio (145.47[Formula: see text]dB), gain bandwidth (4.73[Formula: see text]MHz), phase margin (36.56[Formula: see text]). These figures are significantly improved as compared to conventional OTAs. Analog-to-digital convertor (ADC) is also designed as an application of the proposed OTA. The improvements offered by ADC in terms of power and bandwidth are also compared with state of the art.

A Comprehensive Review and Analytical Comparison of Non-Isolated DC-DC Converters for Fuel Cell Applications

The use of renewable energy sources such as solar photovoltaic, wind, and fuel cells is becoming increasingly prevalent due to a combination of environmental concerns and technological advancements, as well as decreasing production costs. Power electronics DC-DC converters play a key role in various applications, including hybrid energy systems, hybrid vehicles, aerospace, satellite systems, and portable electronic devices. These converters are used to convert power from renewable sources to meet the demands of the load, improving the dynamic and steady-state performance of green generation systems. This study presents a comparison of the most commonly used non-isolated DC-DC converters for fuel cell applications. The important factors considered in the comparison include voltage gain ratio, voltage switch stress, voltage ripple, efficiency, cost, and ease of implementation. Based on the comparison results, the converters have been grouped according to voltage level applications, with low voltage applications being best served by converters such as DBC, DuBC, TLBC, 2-IBC, 1st M-IBC, PSOL, SEPIC, and 1st M-SEPIC owing to their lower cost, smaller size, and reduced switch stress. Medium voltage applications are best suited to converters such as TBC, 1st M-TLBC, 2nd M-TLBC, 4-IBC, 1st M-IBC, 2nd M-IBC, 1st M-PSOL, 2nd M-PSOL, 1st M-SEPIC, and 2nd M-SEPIC, which offer higher efficiency. Finally, high voltage applications are best served by converters such as TBC, 1st M-TBC, 2nd M-IBC, 3rd M-IBC, 3rd M-PSOL, 4th M-PSOL, 2nd M-SEPIC, 3rd M-SEPIC, and 4th M-SEPIC.

A novel ultra low-voltage/low-power rail-to-rail comparator topology in nanoscale CMOS technology

The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and is designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons. However, both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, wide temperature range (from −20 °C to 85 °C) and for random process variations as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on chip prototypes.

Кремниевый с полностью охватывающим затвором полевой нанотранзистор с нелинейной геометрией рабочей области

A silicon CMOS nanotransistor with a cylindrical geometry with a fully enclosing gate with a non-linear geometry of the working area is discussed. Numerical studies of prototypes with a parabolic working area were performed using mathematical modeling using the software environment for instrumental technological modeling TCAD, based on the models of n- and p-type nanotransistors developed by TCAD. An inverter model has been developed for n- and p-type prototypes with an optimized radius ratio of 0.76. At control voltages of 0.6 V and a frequency of 25 GHz, the model predicts a maximum switching delay of 1.0 ps, an active power limit of 0.22 µW, and a static power of 72 pW. The electrophysical characteristics of the n-type prototype with dielectric stacks of gate oxide SiO2-Al2O3 and SiO2-HfO2 are analyzed numerically. The simulation results show that the use of high k stacks has a noticeable effect on key transistor characteristics. Thus, a parabolic nanotransistor architecture with an optimized radius ratio can potentially become a replacement for a cylindrical structure for high-speed low-voltage applications.

A New Tunable Gyrator-C-Based Active Inductor Circuit for Low Power Applications

A new CMOS implementation of active inductor circuit based on the gyrator-C which is suitable for low-voltage and RF applications is presented in this paper. One of the critical features of active inductors which directly affect their quality factor is their series-loss resistance. In this regard, a multi-regulated cascade stage is employed in the new structure which decreases loss. Moreover, by cascading input transistor, the transistors which determine the self-resonance frequency and quality factor will be separated from each other. This results in arranging properties of designed active inductor independently. The configuration of two-stage conventional gyrators is improved which gives the proposed design more opportunities in determining and tuning its characteristics. Also by employing common-source configuration, low conductance nodes are achieved which decrease the ohm-loss of AI. Furthermore, main properties of design can be tuned without affecting each other. The power consumption of the circuit remains as low as 0.62[Formula: see text]mW, then the circuit is suitable for low power applications. The results showed that AI is suitable for RF applications over 0.2–11.8[Formula: see text]GHz frequency range. In order to verify theoretical calculations, simulations are carried out using HSPICE and level 49 parameters (BSIM3v3) in 130[Formula: see text]nm CMOS technology. In addition, Corner and Monte Carlo analyses are considered to prove the efficiency of the circuit against the process variation.

Inductive Wireless Power Transfer Systems for Low-Voltage and High-Current Electric Mobility Applications: Review and Design Example

Along with the technology boom regarding electric vehicles such as lithium-ion batteries, electric motors, and plug-in charging systems, inductive power transfer (IPT) systems have gained more attention from academia and industry in recent years. This article presents a review of the state-of-the-art development of IPT systems, with a focus on low-voltage and high-current electric mobility applications. The fundamental theory, compensation topologies, magnetic coupling structures, power electronic architectures, and control methods are discussed and further considered in terms of several aspects, including efficiency, coil misalignments, and output regulation capability. A 3D finite element software (Ansys Maxwell) is used to validate the magnetic coupler performance. In addition, a 2.5 kW 400/48 V IPT system is proposed to address the challenges of low-voltage and high-current wireless charging systems. In this design, an asymmetrical double-sided LCC compensation topology and a passive current balancing method are proposed to provide excellent current sharing capability in the dual-receiver structures under both resonant component mismatch and misalignment conditions. Finally, the performance of the proposed method is verified by MATLAB/PSIM simulation results.

A new low voltage low power fully differential CMOS class AB current output stage with unique current drive capability

ABSTRACT This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in F T , I outmax , (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications.

A Novel ZVS/ZCS Push-Pull LC Resonant DC-DC Converter for Energy Sources

In this paper, a novel soft switching push-pull LC resonant DC-DC converter for energy sources is presented. In a high step-up converter, the input of primary side possesses low voltage and high current, so the losses caused by the current account for most of the total power loss. At the same time, the high-voltage stress of the high-voltage output components on the secondary side is also a major problem. Therefore, a high-gain isolated push-pull converter with a secondary-side resonant circuit is proposed, so that the primary-side switches have zero voltage switching (ZVS) and the secondary-side diodes have zero current switching (ZCS). The push-pull structure can reduce the number of active switches, so that the total power loss on the primary side can be reduced. The converter has a resonant tank circuit arranged between the secondary side of isolation transformer and the high-voltage output rectification module. The high-voltage output rectifier module adopts a full-bridge architecture suitable for high-voltage coupling connection. The low-side power switching module adopts a push-pull architecture suitable for low-voltage and high-current applications. The resonant tank circuit uses an inductor–capacitor (LC) structure to improve the resonant tank circuit, which achieves soft switching during power transfer, increasing the efficiency of the converter and improving the electromagnetic compatibility. The main advantage of this technology is that the secondary-side leakage inductance of transformer and the resonant capacitance are connected in series to achieve ZVS for switches and ZCS for diodes. Finally, a prototype of a high-gain push-pull resonant converter was established. The converter was operated at a fixed switching frequency of 135 kHz and a duty cycle of approximately 0.5. The efficiency of the converter can reach 97.1% under experimental tests at an output voltage of 400 V and a rated output power of 500 W.

Development of Phase-Shift Full-Bridge Converter With Integrated Winding Planar Two-Transformer for LDC

This study proposes a new phase-shift full-bridge (PSFB) converter with an integrated winding planar two-transformer for a low-voltage dc–dc converter (LDC). An LDC is a dc–dc converter that supplies power to a 12-V auxiliary battery (A_BAT) and loads from the main battery (M_BAT) of electric vehicles (EVs), used in low-voltage and high-current output applications. PSFB converter is widely used as a suitable topology for such systems. In order to improve the power density, the integrated planar magnetics is designed in the proposed PSFB converter. Furthermore, the size of the transformer is optimized considering the footprint and core loss of components. To confirm the validity of the proposed converter, a 2.1-kW prototype LDC with an input voltage range of 400–800 V and an output voltage of 14 V is analyzed, and the operating characteristics are described. The proposed converter achieves a maximum efficiency of 95.4% and a power density of 5.2 kW/L.

Investigation on the conductive properties of single MoO2 nanosheet

Although metallic MoO2 is arising as a new type of conductive transition metal oxide in optoelectrical application. However, the contact and intrinsic conductive properties remain unknown. Here, the contact characteristic and intrinsic conductive of single MoO2 nanosheet grown by CVD method were investigated. It’s found that the contact of Ag with MoO2 was better than that of Au. At low bias condition, the measured intrinsic conductivity of MoO2 is as high as (2.5 ± 1.3) × 104 S/cm. With increasing bias, non-linear behavior in IV characteristic and breakdown behavior is observed due to the contact effect. The supported current density is around 107 A/cm2. The result shows that the MoO2 is a superior conductive transition metal oxide material for the low-voltage application.

Study of ambipolar and linearity behavior of the misaligned double gate-drain dopant-free Nano-TFET: Design and performance enhancement

Work done in this article demonstrates the charge plasma based misaligned double gate-drain doping less tunnel field effect transistor. Designed devices such as perfectly aligned and misaligned, both are optimized by considering the secondary drain in order to investigate ambipolar and linearity behavior. As the work function of secondary drain increases reduction in the ambipolar current is observed with a little degradation in ON state current. It presents a tradeoff between ambipolar current and ON current hence suitable work function of secondary drain is necessary for the proper working of the device. Analog parameters such as ON current, ambipolar current, subthreshold slope, ON to OFF current ratio, ON current to ambipolar current ratio, threshold voltage are analyzed with respect to secondary drain. In order to investigate the device performance for low voltage and low noise applications various linearity parameters such as higher order transconductances, higher order harmonic distortions, higher order intermodulation point and transconductance gain factor have also been demonstrated all the designed structures. The values of ON current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 52 μA, 30 μA, 18 μA and 12 μA respectively. And ambipolar current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 3 pA, 23 pA, 247 pA and 705 pA respectively.

A Transformer Design for High-Voltage Application Using LLC Resonant Converter

The inductor–inductor–capacitor (LLC) resonant converter is a suitable topology for wide output voltage and load range applications with limited circuit parameters. One of the most significant design boundaries of an LLC resonant converter in high-voltage applications is the parasitic capacitance effect of the main circuit components, particularly the transformer and junction capacitances of the secondary rectifier network. Parasitic capacitance effects are much higher in high-voltage applications than in low-voltage applications. Therefore, the use of an LLC resonant converter is limited to high-voltage applications. This study proposes to reduce the capacitive effects of high-voltage transformers and rectification networks with a multi-winding transformer with an integrated rectifier design and to use it in high-voltage applications with the advantages of the LLC resonant converter. For the proposed prototype, comparative experimental measurements were conducted using a conventional scheme. The measurements validate the reliability of the LLC converter for high-voltage applications, improving the output regulation performance while significantly reducing parasitic capacitances.

A Novel Three-Phase Switched-Capacitor Five-Level Multilevel Inverter with Reduced Components and Self-Balancing Ability

This paper proposes a step-up 3-Ф switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology’s advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (VDC), whereas the remaining switches experienced peak output voltage (2VDC) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter’s theoretical justifications and real-time performance.

Single‐stage buck‐boost off‐grid inverter with feedforward control

SummarySince the output voltage accuracy of the off‐grid inverter is low with the proportional‐integral (PI) control and a two‐stage inverter is often used in the low input voltage application, a single‐stage buck‐boost off‐grid inverter with feedforward control is proposed. The proposed inverter consists of a buck‐boost converter and a full‐bridge inverter. The buck‐boost converter operates at high frequency, while the full‐bridge inverter operates at line frequency. Therefore, the intermediate bus voltage is controlled as the unipolar half‐cycle sinusoidal voltage wave to reduce the voltage stress of semiconductors, and film capacitors can be used as intermediate bus capacitors for high reliability and high power density. The operating principle is illustrated. Design guidelines and example are given. The stability analysis and external characteristic analysis are given. A 500‐W proposed inverter is constructed to verify the theoretical analysis.

Fabrication and characterization of a tiny PZT thick-film longitudinal-bending coupled drive vibrator using electrohydrodynamic jet printing

This paper describes a fabrication method of a novel type of micro piezoelectric thick-film longitudinal-bending coupled (LBC) vibrator with a length of 8 mm and thickness of 0.34 mm using electrohydrodynamic jet (E-jet) printing. The LBC micro-vibrator was designed, and a frequency sensitivity analysis of the structural parameters was implemented. When the thickness of the lead zirconate titanate (PZT) thick-film element of the vibrator reached 76 μm, tuning of the composite-mode frequency consistency could be achieved. The micro-vibrator was then fabricated by depositing the PZT thick film directly on the surface of the elastic body using E-jet printing, and the film thickness was flexibly adjusted by tuning the number of prints, thus avoiding the problems of insufficient PZT thin film thickness (≤1 μm) and excessive bulk PZT ceramic volume. Micro-morphological observations showed that the printed thick film was dense and smooth, with a thickness of approximately 76 μm. Furthermore, the vibration mode frequency of the vibrator differed from the test resonant frequencies by only 0.92%, and the vibrator could achieve driving motion with a volume and an excitation voltage approximately one-tenth of that of a bulk piezoelectric motor. Moreover, the unit power density was 0.36 W kg−1 V−1, which is 1.6 times higher than that of a large bulk piezoelectric motor, indicating that the vibrator has good potential for small-space and low-voltage applications.

Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.

A Simulation Optimization Factor of Si(111)-Based AlGaN/GaN Epitaxy for High Frequency and Low-Voltage-Control High Electron Mobility Transistor Application.

The effects of barrier layer thickness, Al component of barrier layer, and passivation layer thickness of high-resistance Si (111)-based AlGaN/GaN heterojunction epitaxy on the knee-point voltage (Vknee), saturation current density (Id-sat), and cut-off frequency (ft) of its high electron mobility transistor (HEMT) are simulated and analyzed. A novel optimization factor OPTIM is proposed by considering the various performance parameters of the device to reduce the Vknee and improve the Id-sat on the premise of ensuring the ft. Based on this factor, the optimized AlGaN/GaN epitaxial structure was designed with a barrier layer thickness of 20 nm, an Al component in the barrier layer of 25%, and a SiN passivation layer of 6 nm. By simulation, when the gate voltage Vg is 0 V, the designed device with a gate length of 0.15 μm, gate-source spacing of 0.5 μm, and gate-drain spacing of 1 μm presents a high Id-sat of 750 mA/mm and a low Vknee of 2.0 V and presents ft and maximum frequency (fmax) as high as 110 GHz and 220 GHz, respectively. The designed device was fabricated and tested to verify the simulation results. We demonstrated the optimization factor OPTIM can provide an effective design method for follow-up high-frequency and low-voltage applications of GaN devices.

A new extended single-switch high gain DC–DC boost converter for renewable energy applications

High-gain DC/DC converters are considered one of the most important components of green energy systems. Large numbers of these converters are used for increasing the voltage gain by using an extreme duty cycle. However, it increases losses and the cost, degrades the system performance, and hence obtains a low efficiency. In this article, a new design of a high-gain DC/DC boost converter is proposed. This converter has the potential to be used in low input voltage applications that need a high voltage gain such as systems powered by solar photovoltaic panels and fuel cells. The new topology is characterized by its simplicity of operation, high voltage gain, better efficiency, continuity of the input current, reduced number of inductors and capacitors, and can be extended to get higher gains. The converter structure, principle of operation, and design consideration of inductors and capacitors are presented in detail. Derivation of power losses and efficiency is presented. A laboratory prototype is implemented, and various experimental tests are given. The achievement of the suggested design is confirmed and compared with other recent high-gain converters.

High Efficiency Over 70% at 3.6-GHz InAlN/GaN HEMT Fabricated by Gate Recess and Oxidation Process for Low-Voltage RF Applications

In this work, high-efficiency InAlN/GaN high electron mobility transistor (HEMT) is fabricated by recess and oxidation process under the gate (RAO) for low-voltage RF applications. Compared with conventional HEMT fabricated on the same heterojunction, RAO-HEMT exhibits a significant decrease in gate leakage, attributed to the thin oxide layer formed around and under the gate as well as adjustment of the location of the peak electric field and confinement of the strong electric field in the oxide. Due to the alleviated electric field as well as adoption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{N}_{{2}}\text{O}$ </tex-math></inline-formula> for plasma treatment, suppressed RF dispersion including the extremely low current collapse and negligible knee voltage walkout is obtained for RAO-HEMT. Although RAO-HEMT delivers lower saturation current as the result of the partial oxidation of the barrier under the gate, it shows a similar ON-resistance to conventional HEMT, which contributes to the reduction in knee voltage. Besides, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}/{f}_{\text {MAX}}$ </tex-math></inline-formula> is achieved for RAO-HEMT, as the result of the higher dc transconductance and suppressed RF transconductance collapse as well as larger output resistance. Eventually, benefiting from the improvement in gate leakage, RF dispersion, knee voltage, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> by RAO, RAO-HEMT delivers both higher power-added-efficiency (PAE) and output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {OUT}}$ </tex-math></inline-formula> ) than conventional HEMT. At 3.6 GHz, RAO-HEMT provides a high PAE of 71% (74%) at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DS}}}$ </tex-math></inline-formula> of 6 V (9 V), which performs better than most of the existing Si, GaAs, or GaN RF devices in PAE, revealing the great potential of InAlN/GaN RAO-HEMT in low-voltage low-power consumption RF applications.