A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications

Abstract

A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-voltage and low-power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock transitions with footed differential latches and the same area as a conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at a low supply voltage regime, achieving wide-range voltage scalability (1–0.3 V). The measurement results with a test chip fabricated in 28-nm CMOS technology show that power consumption is reduced by 64%/56% with a 0%/10% activity ratio at 1 V compared to that of a TGFF. All 100 dies from five process corners were functional with supply voltage as low as 0.28 V.