A bootstrapped CMOS circuit technique for low-voltage application

Abstract

Novel low-voltage CMOS logic family, called bootstrapped latched CMOS logic (BLCL), and demand-on-boosting bootstrapped latched CMOS logic (DB-BLCL) are proposed for low-voltage and low-power applications. These circuits improve operation speed at low supply voltage region for driving a large capacitive load by boosting internal nodes beyond the power supply or below the ground using a single bootstrap capacitor. They provide larger bootstrap voltages than the conventional CMOS bootstrap circuit by eliminating charge loss from the bootstrap nodes. Moreover, each bootstrap node in DB-BLCL circuit is boosted on demand depending on the input and output values to minimize the average power consumption and the drivers are transiently overdriven during only the output transition period for device reliability. These circuits were designed using 0.35 /spl mu/m CMOS process technology. The comparison result indicates that BLCL provides switching speed improvements of 15-30% with comparable power consumption as compared to the conventional bootstrapped circuit. In addition, DB-BLCL obtains the same switching speed improvement as BLCL with 33% less power consumption due to unique demand-on bootstrapping capability.