A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications

Abstract

A Static Contention-free Differential Flip-Flop (SCDFF) is presented in 28nm CMOS for low voltage and low power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock toggling with footed differential latches, while keeping same area with conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at low supply voltage regime, achieving wide-range voltage scalability (1V to 0.3V). Measurement results with test chip fabricated in 28nm CMOS technology show that power consumption is reduced by 64 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> /56 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> with 0%110% activity at IV, compared to the TGFF. All 100 dies from 5 process corners were functional with supply voltage as low as 0.28V.