CMOS Applications Research Articles

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

Impact of Rh, Ru, and Pd Leads and Contact Topologies on Performance of WSe2 FETs: A First Comparative Ab Initio Study.

2D field-effect transistors (FETs) fabricated with transition metal dichalcogenide (TMD) materials are a potential replacement for the silicon-based CMOS. However, the lack of advancement in p-type contact is also a key factor hindering TMD-based CMOS applications. The less investigated path towards improving electrical characteristics based on contact geometries with low contact resistance (RC) has also been established. Moreover, finding contact metals to reduce the RC is indeed one of the significant challenges in achieving the above goal. Our research provides the first comparative analysis of the three contact configurations for a WSe2 monolayer with different noble metals (Rh, Ru, and Pd) by employing ab initio density functional theory (DFT) and non-equilibrium Green's function (NEGF) methods. From the perspective of the contact topologies, the RC and minimum subthreshold slope (SSMIN) of all the conventional edge contacts are outperformed by the novel non-van der Waals (vdW) sandwich contacts. These non-vdW sandwich contacts reveal that their RC values are below 50 Ω∙μm, attributed to the narrow Schottky barrier widths (SBWs) and low Schottky barrier heights (SBHs). Not only are the RC values dramatically reduced by such novel contacts, but the SSMIN values are lower than 68 mV/dec. The new proposal offers the lowest RC and SSMIN, irrespective of the contact metals. Further considering the metal leads, the WSe2/Rh FETs based on the non-vdW sandwich contacts show a meager RC value of 33 Ω∙μm and an exceptional SSMIN of 63 mV/dec. The two calculated results present the smallest-ever values reported in our study, indicating that the non-vdW sandwich contacts with Rh leads can attain the best-case scenario. In contrast, the symmetric convex edge contacts with Pd leads cause the worst-case degradation, yielding an RC value of 213 Ω∙μm and an SSMIN value of 95 mV/dec. While all the WSe2/Ru FETs exhibit medium performances, the minimal shift in the transfer curves is interestingly advantageous to the circuit operation. Conclusively, the low-RC performances and the desirable SSMIN values are a combination of the contact geometries and metal leads. This innovation, achieved through noble metal leads in conjunction with the novel contact configurations, paves the way for a TMD-based CMOS with ultra-low RC and rapid switching speeds.

Influence of growth temperature on the magnetization dynamics of sputtered CoFeB thin films on various substrates and their microwave device functionality

In the present investigation, sputtering growth of 100 nm thick Co40Fe40B20 (CoFeB) film has been investigated in a low temperature range from room temperature (RT) to 400 ℃ on silicon (Si), silicon dioxide (Si/SiO2), and sapphire (Al2O3) substrates. The film surface morphology, static and dynamic magnetization were measured as a function of growth temperature and substrate. The grown films were further tested as a potential material for microwave device functionality in terms of filter and phase shifter. Surface roughness was lowest for the film grown on Si/SiO2 substrate at 200 ℃ (0.39 nm) measured from atomic force microscopy. Static magnetic properties measured by tracing magnetic hysteresis loop suggest a soft magnetic behaviour with in-plane magnetic anisotropy. Film saturation magnetization increases with the increase in growth temperature up to 200 ℃ and then decreases from 200 ℃ to 400 ℃. This suggest that the sputtering growth from room temperature to 200 ℃ offer a moderate to low interfacial stress resulting in low defects density. Gilbert damping constant (αeff) of the thin film is obtained from the ferromagnetic resonance measurements in a broad band of microwave frequencies. Damping was lowest (5.4×10−3) in the film grown at 200 ℃ on the Si/SiO2 substrate which correlates with the roughness and magnetization data. A low value of αeff is desirable for a material to be used in energy efficient spintronics and magnonic applications. The CoFeB films were also utilized in prototype microwave band-stop filter and phase shifter device applications. The filter has been tested in the frequency range from 6GHz to 25GHz with an applied magnetic bias up to 4.0 kOe. The frequency tunability with respect to the applied magnetic bias measured to be around 3.64 GHz/kOe. The maximum attenuation of −4dB was observed for the film grown on Si/SiO2 substrate at 200 ℃. Whereas, phase shifter fabricated on Si/SiO2/CoFeB film grown at 200 ℃ shows a differential phase shift up to 75°/cm. These results indicates that the CoFeB film deposited at low growth temperature can be a potential material in spintronics and CMOS applications where low temperatures are required for device fabrications.

Ultrashort channel MoSe2 transistors with selenium atoms replaced at the interface: first-principles quantum-transport study

Realizing n- and p-type transition metal dichalcogenide (TMD)-based field-effect transistors for nanoscale complementary metal oxide semiconductor (CMOS) applications remains challenging owing to undesirable contact resistance. Quantumtransport calculations were performed by replacing single-sided Se atoms of TMD near the interface with As or Br atoms to further improve the contact resistance. Here, partial selenium replacement produced a novel interface with a segment of metamaterial MoSeX (Pt/MoSeX/MoSe2; X = As, Br). Such stable metamaterials exhibit semi-metallicity, and the contact resistance can be thus lowered. Our findings provide insights into the potential of MoSe2-based nano-CMOS logic devices.

Analysis of p-Type Doping in Graphene Induced by Monolayer-Oxidized TMDs.

Doping is one of the most difficult technological challenges for realizing reliable two-dimensional (2D) material-based semiconductor devices, arising from their ultrathinness. Here, we systematically investigate the impact of different types of nonstoichiometric solid MOx (M are W or Mo) dopants obtained by oxidizing transition metal dichalcogenides (TMDs: WSe2 or MoS2) formed on graphene FETs, which results in p-type doping along with disorders. From the results obtained in this study, we were able to suggest an analytical technique to optimize the optimal UV-ozone (UVO) treatment to achieve high p-type doping concentration in graphene FETs (∼2.5 × 1013 cm-2 in this study) without generating defects, mainly by analyzing the time dependency of D and D' peaks measured by Raman spectroscopy. Furthermore, an analysis of the structure of graphene sheets using TEM indicates that WOx plays a better protective role in graphene, compared to MoOx, suggesting that WOx is more effective for preventing the degradation of graphene during UVO treatment. To enhance the practical application aspect of our work, we have fabricated a graphene photodetector by selectively doping the graphene through oxidized TMDs, creating a p-n junction, which resulted in improved photoresponsivity compared to the intrinsic graphene device. Our results offer a practical guideline for the utilization of surface charge transfer doping of graphene toward CMOS applications.

Advanced CMOS Devices and Applications

The persistent scaling of transistor dimensions has marked an era characterized by a fourfold increase in transistor density and a twofold boost in electrical performance every 2–3 years, effectively reducing their cost per function [...]

A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications

We propose a new technology and design platform using combined common gate N/PFET CFET as basic element for CMOS circuit applications. Two CFET unit structures, namely common gate (CG) and N-gate (NG), are identified to form base design elements. Through the two units, all circuit logic functions in standard cell library and SRAM can be realized without significant process complication. A Multi-gradient Neural Network (MNN) based SPICE compact modeling methodology is developed for these CFET units. As an example, MNN model generation is illustrated for CG with the output matching well with the TCAD data within and beyond the range of model extraction. Circuit simulations are exercised using the MNN models and demonstrated successfully the expected circuit functionalities. As the CFET technology be adopted as mainstream in future, this novel design framework proposed would enable efficient logic design.

Germanium surface cleaning and ALD of a protective boron nitride overlayer

Germanium exhibits superior hole and electron mobility compared with silicon, making it a promising candidate for replacement of silicon in certain future CMOS applications. In such applications, achieving atomically clean Ge surfaces and the subsequent deposition of ultrathin passivation barriers without interfacial reaction are critical. In this study, we present in situ x-ray photoelectron spectroscopy (XPS) investigations of hydrocarbon removal from the Ge surface utilizing atomic oxygen at room temperature, as well as removal of hydrocarbons and of germanium oxide (GeO2) through atomic hydrogen treatment at 350 °C. Subsequently, atomic layer deposition (ALD) was used to create a protective layer of hexagonal boron nitride (h-BN) with an average thickness of 3 monolayers (ML). Tris(dimethylamino)borane and ammonia precursors were utilized at 450 °C for the deposition process. Intermittent in situ XPS analysis during ALD confirmed h-BN growth, stoichiometry, and the absence of interfacial reaction with Ge. XPS analysis after subsequent exposure of the Ge film with a h-BN overlayer of ∼9 Å average thickness to 7.2 × 104 l of atomic O (O3P) at room temperature yielded no evidence of Ge oxidation, with only the surface layer of the h-BN film exhibiting oxidation. These results present a practical and scalable route toward the preparation of clean Ge surfaces and subsequent deposition of protective, nanothin h-BN barriers for subsequent processing.

A systematic study on complementary metal-oxide semiconductor technology (CMOS) and Internet of Things (IOT) for radioactive leakage detection in nuclear plant

Although nuclear power plants produce about 20% of India's power, the risk posed by radioactive leakage is considerable. Radiation leakage detection devices must be installed in all nuclear power plants to ensure that avoidable catastrophes never occur again and that the loss of human life is prevented. A safe atmosphere for inhabitants and workers may be ensured by keeping a consistent radiation level in all applications that use radioactive material. Complementary Metal-Oxide Semiconductor technology, or CMOS, uses complementary and symmetrical MOSFETS for logic-based functions in various applications, such as analog circuits (CMOS sensors). The Internet of Things (IoT) extends the power of the Internet beyond computing devices to a multitude of other things, processes, and environments. The main objective of this paper is to find a better and more creative solution for radioactive leakage detection techniques over present-day techniques. In this paper, the Authors aim to integrate CMOS and IOT applications for radioactive leakage detection methods on an industrial level. Within this paper, we have given brief descriptions of CMOS and IoT with their types, functions, methodology, and applications. CMOS is considered to be the most sophisticated and precise technology that can be employed to measure radiation leaks of all types (alpha rays, beta rays, gamma rays, and neutrons). With the help of IOT, massive disasters can be averted using complex alert systems. A well-coordinated combination of the two technologies has the potential to vastly increase leak detection potential and consistency. The study's major goal is to develop new and improved technology for detecting released radiation in the industry in order to obtain real-time information about the material leaked, as well as the location of the leak and the quantity of leakage that occurred, in order to reduce the danger of a natural catastrophe.

Wearable and Noninvasive Device for Integral Congestive Heart Failure Management in the IoMT Paradigm.

Noninvasive remote monitoring of hemodynamic variables is essential in optimizing treatment opportunities and predicting rehospitalization in patients with congestive heart failure. The objective of this study is to develop a wearable bioimpedance-based device, which can provide continuous measurement of cardiac output and stroke volume, as well as other physiological parameters for a greater prognosis and prevention of congestive heart failure. The bioimpedance system, which is based on a robust and cost-effective measuring principle, was implemented in a CMOS application specific integrated circuit, and operates as the analog front-end of the device, which has been provided with a radio-frequency section for wireless communication. The operating parameters of the proposed wearable device are remotely configured through a graphical user interface to measure the magnitude and the phase of complex impedances over a bandwidth of 1 kHz to 1 MHz. As a result of this study, a cardiac activity monitor was implemented, and its accuracy was evaluated in 33 patients with different heart diseases, ages, and genders. The proposed device was compared with a well-established technique such as Doppler echocardiography, and the results showed that the two instruments are clinically equivalent.

Spin–orbit torque flash analog-to-digital converter

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

Symmetric and Excellent Scaling Behavior in Ultrathin n‐ and p‐Type Gate‐All‐Around InAs Nanowire Transistors

AbstractComplementary metal‐oxide‐semiconductor (CMOS) field‐effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µe than silicon but suffers from a much lower hole mobility µh (µe/µh = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum‐transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub‐2‐nm‐diameter gate‐all‐around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short‐channel effects are effectively depressed in the symmetric n‐ and p‐type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.

Germanium and silicon-based nanohole LWIR metalens design and fabrication

Thermal imaging, particularly LWIR imaging, has several applications in commercial and security systems. The fundamental problem with the development of metalens is the lack of appropriate materials for LWIR applications. The development of silicon metalens is hampered by the material’s own LWIR spectral band absorption, although silicon is the ideal material for lithography due to its widespread use in CMOS applications. In this study, metalens working on LWIR spectral band has been designed and fabricated using the highly suitable material germanium and low-cost silicon. The focusing and imaging capacity of two types of metasurfaces has been investigated, and a comparison of the results has been presented in the paper.

Systematic Interpretation of Time Effect on Negative Capacitance of Ferroelectrics Based on Electrostatics and Charge Dynamics

Negative capacitance (NC) effects in ferroelectric (FE) films have attracted intensive attention recently in terms of both polarization kinetics modeling and low-power CMOS applications. Its physical origin, however, is controversial because the experimentally observed NC effects are different from the initial concept, particularly on the frequency/voltage dependence and hysteresis. Recently, we have proposed an electrostatic model, with which the NC effect with hysteresis and voltage dependence in FE/paraelectric (PE) stacks in dc mode is explained from a viewpoint of polarization switching. Based on this, in this work, the NC effect in the dimension of time in both FE/PE and FE capacitor–resistor (FE-R) circuit is analytically formulated and experimentally studied by comprehensively considering the dynamics of polarization switching, charge communication with power supply, and charge leaking through the capacitor. Our results suggest that such NC effects only occur in a time window in both systems and a competition between FE switching and charge compensation is the key to determine the time window. Thus, a systematic understanding is accomplished to explain most of the phenomenon associated with NC effects in FEs.

A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS

This paper presents a 28-GHz wideband power amplifier (PA) with the dual-pole tuning superposition technique for 5G applications in a 55-nm RF CMOS. The PA employs a four-stage pseudo-differential structure together with the two-way combining approach to enhance the power gain. Transmission-line transformer (TLT) matching networks are proposed in the PA for not only performing the impedance matching, but also tuning the peak gains of the four stages to two different pole frequencies. The dual-pole frequencies are eventually superposed to improve the bandwidth and gain. Meanwhile, techniques of capacitance neutralization, load-pulling, and power combination are adopted for power stages to improve the output power and efficiency significantly. Biased at the class-A mode by a supply voltage VDD of 1.5 V, the fabricated PA exhibites the measured peak small-signal gain (S21) of 21.9 dB and power gain (PG) of 20 dB at 28 GHz. The measured performances of saturated output power (Psat) of 15.4–16.8 dBm, output 1-dB compression point (OP1dB) of 12–13.5 dBm, and power added efficiency (PAEP1dB) of 11%–14.7% are achieved over the bandwidth of 24–30 GHz, featuring wideband linearity/PAE. The chip occupies a core area of 1.5 × 0.6 mm2.

(Dielectric Science & Technology Thomas Callinan Award) Materials and Processes As Enablers for Moore Moore and Beyond Moore Technologies

In this presentation, an overview will be presented of historic and recent developments achieved w.r.t. materials and processes that enabled continued performance scaling of CMOS and beyond CMOS applications. Starting from early high-k work. For decades, thermal oxidation of crystalline Silicon into SiO2 has been the gate oxide material in CMOS technology. Miniaturization for performance improvement, required the gate dielectric to decrease in thickness to support the required increase in capacitance (per unit area) and drive current (per device width). Early 2000, the thickness scaled below 1.5 nm, causing drastically increased leakage currents, high power consumption and reduced device reliability. Replacing the SiO2 gate dielectric with a high-κ (dielectric constant) material allows increased gate capacitance without the associated leakage effects. Activities involved the unit process step development of dielectric and metal deposition processes, advanced interface preparation, electrical and physical characterization and wet and dry etch process development. In a second section, emphasis will be on emerging nanomaterials. Nanotechnology is defined as the manipulation of matter with at least one dimension sized from below 100nm, thus all CMOS activities are functional nanotechnology. The latter concentrated initially on Graphene, but extended further towards Transition Metal Dicalchogenide Materials. Emphasis of the work will be on growth, functionalization, dielectric passivation and doping of these materials. Lastly, expanding on the nanomaterial know-how also progress with regard to low-k dielectrics, area selective deposition processes (for bottom-up lithography) and application of nanochemistry research for photoresist material screening, where chemical interactions at the nanoscale, related to the EUV lithography (radiation chemistry) are hampering the pattern scaling.Throughout the presentation, recognition will be given to people (PhD students) that contributed to this work and the presentation is also in honor of Prof Dolf Landheer and Professor Samares Kar with whom I organized my first ECS symposium.

Device operation and physical mechanism of asymmetric junctionless tunnel field-effect transistors designed to suppress coupled short-channel/short-drain effects and promote on-current switching for ultralow-voltage CMOS applications

Scaled tunnel field-effect transistors (TFETs) endure severe short-channel and short-drain effects caused by direct source-to-drain and body-to-drain tunneling. This study numerically examined a Si-based asymmetric junctionless TFET (AJ-TFET) architecture for suppressing coupled short-channel and short-drain effects in and improving the on-current switching of TFET devices for ultralow-voltage CMOS applications. The junctional drain/body facilitates the extending of the off-state tunnel barrier into the drain, enhancing robustness against short-channel and short-drain effects. The junctionless source/body can minimize lateral coupling and thus lead to efficient switching in a TFET, thus generating steep on–off switching swings. The results revealed that in contrast to conventional PIN-TFETs, the AJ-TFET evaluated in this study exhibited considerably lower swing levels and higher current levels. The voltage-scaled AJ-TFET retained excellent subthreshold behaviors and short-channel robustness, offering adequate on-current levels along with minimized leakage levels. Incorporating high-k gate dielectrics into the devices enabled extra on-current boosting and swing minimization, further extending the deep-swing, high-current operation region. Because of their excellent on–off switching and on-current enhancement, the extremely scaled AJ-TFET could operate adequately at low gate and drain voltages (0.3–0.5 V); therefore, they are promising candidates for use in ultralow-voltage energy-efficient applications.

RF performances at cryogenic temperature of inductors integrated in a FDSOI technology

This paper investigates the RF performances of octagonal inductors integrated in a Fully Depleted Silicon On Insulator (FD-SOI) technology at cryogenic temperature. The RF performances characterization of passive and active components is a first necessary step towards the design of RF circuits optimized for cryogenic CMOS applications. Among passive components, inductors are key to design low noise amplifier needed for instance in qubits read-out circuit. First, the experimental set-up and the experimental protocol is presented in detail. Then inductance with 0.5nH to 4nH values are characterized in frequency from room temperature down to 4.2 K and modelled by a lumped elements circuit. We used a simple RLC circuit to describe the self-resonance behaviour. A calculation is proposed for the inductance and the capacitance, whereas the resistance is extracted by DC measurements. This circuit description is improved by including coil proximity and skin effects. We observed that the quality factor is improved by a factor of two at low temperature, thanks to the metal resistivity decreases, in qualitative agreement with DC measurements. We also discussed the limits of the proposed model.

Performance tunability of field-effect transistors using MoS2(1−x)Se2x alloys

Ultra-thin channel materials with excellent tunability of their electronic properties are necessary for the scaling of electronic devices. Two-dimensional materials such as transition metal dichalcogenides (TMDs) are ideal candidates for this due to their layered nature and great electrostatic control. Ternary alloys of these TMDs show composition-dependent electronic structure, promising excellent tunability of their properties. Here, we systematically compare molybdenum sulphoselenide (MoS2( 1−x )Se2x ) alloys, MoS1Se1 and MoS0.4Se1.6. We observe variations in strain and carrier concentration with their composition. Using them, we demonstrate n-channel field-effect transistors (FETs) with SiO2 and high-k HfO2 as gate dielectrics, and show tunability in threshold voltage, subthreshold slope (SS), drain current, and mobility. MoS1Se1 shows better promise for low-power FETs with a minimum SS of 70 mV dec−1, whereas MoS0.4Se1.6, with its higher mobility, is suitable for faster operations. Using HfO2 as gate dielectric, there is an order of magnitude reduction in interface traps and 2× improvement in mobility and drain current, compared to SiO2. In contrast to MoS2, the FETs on HfO2 also display enhancement-mode operation, making them better suited for CMOS applications.

A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design

This article presents a broadband power amplifier (PA) with a distributed-balun output network that provides the PA optimum load impedance over a wide bandwidth. The proposed output network comprises two coupled-line sections and absorbs the device output capacitance. It employs a scalable coupled-line modeling approach that captures both the magnetic (inductive) and electric (capacitive) couplings between windings with fewer parameters and supports a rapid design process. Closed-form design solutions, design space limitations, bandwidth limits, and design tradeoffs are derived and analyzed comprehensively. Its extension to differential output and common-mode response is also discussed in detail. As a proof of concept, a prototype PA is implemented for multiband fifth-generation (5G) applications in 45-nm SOI CMOS. With no biasing retuning or network reconfiguration, the PA consistently achieves >19.1 dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> , >37.3% peak power-added efficiency (PAE), 17.8-19.6 dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , and 36.6%-44.3% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P1dB</sub> over 24-40 GHz, verifying the truly wideband large-signal matching. The PA demonstrates 5G new radio (NR) frequency range 2 (FR2) modulation signals over 24-42 GHz, covering n257/n258/n260 5G bands. For 5G NR FR2 800-MHz 2-CC 64-QAM signals (11.78-dB PAPR), the PA achieves 11.3-dBm/16.6% average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> /PAE with -25.1-dB rms EVM at 28-GHz and 10.2-dBm/13.6% average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> /PAE with -25.1-dB rms EVM at 37 GHz.