Annealed Polycrystalline Silicon Research Articles

Characterization of laser annealed polycrystalline silicon films on various substrates

The structure and property of eximer laser annealed poly-Si films on various substrate materials such as MoW, Cr, $$ SiO_2 $$ were studied. It was found that the crystallinity of the film depended on the recrystallization energy density and substrate materials. The crystallinity of the film on $$ SiO_2 $$ substrate was the highest quality, and the higher the thermal conductivity of the substrate, the poorer the crystallinity of the poly-Si films at the same laser energy density. In the lower laser energy region than optimum, the grain size and surface roughness were increased with increasing laser power due to the increase of the crystallinity and decreased intrinsic stress. On the other hand, in the higher power region than optimum, with the increase of laser power, X-ray intensity and grain size were decreased due to the fast solidification velocity. There was no metal diffusion into poly-Si film but small amount of Si, less than 3 atomic percent, diffused into the metal film during the recrystallization process.

Crystal Growth of Laser Annealed Polycrystalline Silicon as a Function of Hydrogen Content of Precursors

ABSTRACTThe influence of hydrogen in a precursor on excimer laser crystallization behavior was investigated. The crystal orientation and lattice constant of polycrystalline silicon films were analyzed by X-ray diffraction measurement. An intensity ratio of 111 to 220 was used as an index of the (111) preferred orientation. A randomly oriented film with an index of 2 at lower energy density changed to the highly (111) oriented phase with an index of more than 15 at higher energy density. It was observed in the PE-CVD films that increasing the hydrogen in the precursor films decreased the orientation index. The lattice constant of the laser-annealed PE-CVD silicon was found to be larger than that of the PVD silicon and to decrease with an increase in laser energy density. The network structure of as-deposited PVD film with less hydrogen content was denser than that of as-deposited PE-CVD. The network structure of the precursor strongly affected the crystal growth, and the structure of the ELC poly-Si was still affected by the precursors, even though the hydrogen content decreased after laser annealing.

Effect of excimer laser annealing on the structural and electrical properties of polycrystalline silicon thin-film transistors

The structural and electrical properties of excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated in relation to the laser energy density. The devices were fabricated on 50 nm thick polysilicon films prepared by excimer laser crystallization (ELA) of amorphous silicon or by a combined solid phase crystallization (SPC) and ELA process. The structural properties of the polysilicon films have been investigated by transmission electron microscopy analysis. The effective density of states distributions in the polysilicon films and in the oxide traps near the oxide/polysilicon interface have been determined from low frequency noise measurements. The TFT performance parameters are compared with respect to their correlation with the structural properties of the polysilicon films and their electrically active defects, the basic variables being the starting material (amorphous silicon or SPC polysilicon) and the laser energy density.

Electrical and noise properties of thin-film transistors on very thin excimer laser annealed polycrystalline silicon films

Thin-film transistors, fabricated on polycrystalline silicon films prepared by combined solid phase crystallization of amorphous silicon and excimer laser annealing processes, have been investigated by electrical and low frequency noise measurements in relation to the active layer thickness and the laser energy density. The device performance is improved with increasing the laser energy density until a critical value where the film is completely melted. By decreasing the active layer thickness from 50 to 25 nm, although the subthreshold characteristics are improved, the electron mobility and the threshold voltage are degraded. The noise data indicate that the degradation is related to electron trapping in both gate and substrate oxide interface traps.

Effect of multiple scans and granular defects on excimer laser annealed polysilicon TFTs

A thorough investigation of excimer laser annealed polycrystalline silicon thin film transistors fabricated from single and multiple laser scan processes has been completed. Our results show that even though multiple scans can enhance the grain size in the polycrystalline silicon film, the production of intragrain defects and interface trapping states have adverse effects on the performance of the corresponding devices and in particular, on the leakage current, threshold voltage and subthreshold swing. Further investigation revealed substantial changes in the source-drain current activation energy, as a function of the number of scans. Using our experimental data, coupled with theoretical analysis, we were able to examine to what degree intragrain and grain boundary mobilities determine the overall field effect mobility of the device. A transition region, based on the grain boundary barrier height, was identified separating annealing conditions for which the carrier scattering in the grains or the carrier scattering at the grain boundaries dominated the conduction process.

Comparison of the stress between rapid thermal annealed and excimer laser annealed polycrystalline silicon thin films

Characteristics of polycrystalline silicon films with large substrate such as 50 mm × 50 mm, crystallized by using furnace annealing (FA), multi-step rapid thermal annealing (MSRTA) and excimer laser annealing (ELA) methods, have been investigated. In order to characterize the residual stress in crystalline silicon on corning 7059 glass, polarized Raman spectroscopy were measured for those various annealing methods and at various substrate temperatures. We observed that the polycrystalline Si films, crystallized by ELA, have a high crystalline volume fraction, residual stress and equiaxial crystal growth. On the other hand, silicon films crystallized by FA and MSRTA have a low compressive stress and dendritic structure, which are due to thermal relaxation. These Si films have a broad hump around 480 cm −1 which indicates the existence of amorphous phase silicon. The magnitudes of stresses of FA and MSRTA are 4.07 × 10 9 and 4.46 × 10 9 dyne cm −2, respectively and the magnitude of stress of laser annealing decreases from 1.35 × 10 10 to 8.58 × 10 9 dyne cm −2 with increasing the substrate temperature from room temperature to 400°C.

Xrd and Xtem Investigation of Polycrystalline Silicon Carbide on Polycrystalline Silicon

AbstractAtmospheric pressure chemical vapor deposition (APCVD) was used to grow silicon carbide (SiC) on as-deposited and annealed polycrystalline silicon (polysilicon) films which were deposited on oxidized Si wafers. X-ray diffraction (XRD) reveals that SiC films grown on asdeposited polysilicon have a (110) orientation. XRD performed on as-deposited polysilicon before and after SiC growth reveals that the orientation of polysilicon changes from (110) to a mixture of (110) and (11) during growth of 2 μm-thick SiC films. Cross-sectional transmission electron microscopy (XTEM) images of the SiC/polysilicon interface show that the SiC appears to be unaffected by the recrystallization of the underlying polysilicon during the SiC growth. XRD from samples of SiC grown on annealed polysilicon show that both films have (110) and (111) orientations. For SiC films grown on annealed polysilicon substrates, XTEM images show that the crystallinity of the annealed polysilicon substrate does not significantly change during SiC growth. Furthermore, an investigation of the SiC/annealed-polysilicon interface using selected area diffraction (SAD) shows that an epitaxial relationship exists between the polysilicon and SiC grains.

Investigation of Pre-Tungsten Silicide Deposition Wet Chemical Processing

ABSTRACTRemoving the native oxide from the poly-Si surface prior to WSix deposition is essential for achieving high quality silicides as well as sufficient film adhesion, particularly after high temperature anneal or oxidation. Contact angle studies have been used to determine initial and time-dependent surface characteristics of several types of silicon surfaces following immersions in HF-based etchants for varying amounts of time. The morphological characteristics of the surfaces before and after exposure to etchants, as well as the relative etch rates and wetting capabilities of the etchants have been used to explain the following results: With respect to initial contact angle studies, the implanted & annealed polycrystalline silicon surface has the lowest contact angle followed by polycrystalline and monocrystalline surfaces. Longer immersion times yield lower initial contact angles. The 0.1% lightly-buffered HF solution results in the highest contact angle followed by the 1% buffered HF solution with surfactant, and the 1% HF solution. With respect to contact angle changes during ambient air exposure time, the asdeposited polycrystalline silicon surface is most stable followed by monocrystalline, and implanted & annealed polycrystalline silicon surfaces. Longer immersion times improve surface stability while the 0.1% lightly-buffered HF solution results in the most stable surface followed by the 1% buffered HF solution with surfactant, and the 1% HF solution.

Measurement of Carbon Concentration in Polycrystalline Silicon Using FTIR

The carbon concentration in polycrystalline silicon produced via the Siemens process, the hydrogen reduction of trichlorosilane, was evaluated using FTIR. Samples measured included: as grown polycrystalline silicon, high‐temperature annealed polycrystalline silicon, and float zone refined single‐crystalline silicon. It was found that infrared measurements made on high‐temperature annealed polycrystalline silicon samples display similar carbon concentrations as those obtained on float zone refined single‐crystalline silicon samples. Little, if any, evidence exists for the occurrence of significant amounts of interstitial carbon in low carbon concentration polycrystalline silicon material. High‐temperature annealing of polycrystalline silicon results in improved spectrum quality, and therefore, reduces the detection limit and improves the accuracy of the carbon measurement in polycrystalline silicon. A liquid helium sample Dewar was successfully used for cryogenic temperature measurement resulting in further improvement in sensitivity.

Equilibration of nonstoichiometric Ta-Si deposits on polycrystalline silicon at high temperatures

The formation of tantalum disilicide from either a metal- or silicon-rich amorphous film was studied to provide information on the kinetics of phase formation and the corresponding details of atom diffusion. A thin-film structure consisting of ∼3000 Å of cosputtered Ta-Si on ∼4000 Å of annealed polycrystalline silicon (which will be referred to as ‘‘silicon’’) on ∼1250 Å of silicon dioxide was deposited over monocrystalline Si(100) wafers. The deposition variables probed were (1) arsenic doped versus undoped silicon, (2) Si/Ta atom ratios of 3.2 and 1.3, and (3) capping silicon dioxide layers versus no capping present during the anneals. One hour anneals were performed in vacuum between 850 and 1000 °C at 50 °C intervals. Rutherford backscattering spectrometry and transmission electron microscopy measurements show that the metal-rich film consumes an appropriate amount of silicon to form the stable tantalum disilicide phase even at the lowest anneal temperature. On the other hand, the rate of formation of TaSi2 from the Si-rich film is affected by both the presence of capping oxide and dopant in the underlying silicon. The main mechanism for Si ejection in the uncapped specimens is evaporation from the surface. In the capped specimens, the main Si loss mechanism is growth of a Si layer between the silicon and tantalum disilicide. In this case, formation of TaSi2 and simultaneous growth of the Si layer is enhanced by the presence of arsenic dopant.

High-voltage TFT fabricated in recrystallized polycrystalline silicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 mu m. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage. >

Properties of Gallium Implanted Furnace and Rapidly Annealed Polycrystalline Silicon

ABSTRACTPolycrystalline silicon films have been amorphized by implantation with 100keV Ga ions of doses 0.3 and 6×1015cm−2. These films were subsequently recrystallized using either a furnace for longer times lower temperature (∼30 mins, 600° C) or rapid thermal processing (RTP) for shorter times higher temperatures ( ≤ 30 sec, 800° C, 900° C) in an endeavour to suppress any long range movement of the Ga during the anneal phase. It is found that for both the furnace and RTP for temperatures ≤ 800°C no significant movement is observed and that the lower temperature anneal for the highest dose produces the highest electrical conductivity. By contrast however, annealing at 900° C, even though the initial conductivity is higher than for any other anneal we observe a significant reduction with time and extremely rapid movement of the dopant species throughout the original poly layer. An initial rationale for this behaviour is proposed in terms of a liquid phase transformation during annealing.

Effects of Processing on Characteristics of 10–15 nm Thermally Grown SiO2 Films

Thin uniform films, 10–15 nm in thickness, were grown at 800°C in wet ambients. Good dielectric breakdown distribution was observed for films as thin as 10 nm. An barrier height of was obtained for these thin films. The presence of positive charge around the electrode, induced by processing, was found to cause abnormal capacitance‐voltage (C‐V) traces and erroneous results on measurements of minority carrier lifetime by the pulse C‐V technique. Four types of current‐voltage (I‐V) behavior were observed. The generation of traps at high fields was found to be a defect related behavior. A degradation of breakdown distribution for thin films was observed after these films were either dipped in a solution containing and , or subjected to excessive annealing. For annealed polycrystalline silicon structures, an upward grain growth was found, and a pile‐up of phosphorus at the interface was detected.

Electrical properties and grain size of phosphorus in situ doped and cw laser annealed polycrystalline silicon films : T. Ternisien d'Ouville et al,J Appl Phys, 53 (7), 1982, 5086–5092

Electrical properties and grain size of phosphorus in situ doped and cw laser annealed polycrystalline silicon films : T. Ternisien d'Ouville et al,J Appl Phys, 53 (7), 1982, 5086–5092

Stochastic model for grain size versus dose in implanted and annealed polycrystalline silicon films on SiO2

160-nm polycrystalline silicon films were implanted at room temperature with 100-keV silicon ions and subsequently annealed. The final grain size was found to increase with implant dose. A model is presented here to account for the dose dependence of the grain size. Three mechanisms were presumed to account for the final grain size: statistical variations of area coverage by the implanted ions, ion channeling, and spontaneous nucleation. Model parameters were successfully fit to the experimental data.

Analysis of laser annealed polycrystalline silicon thin-film transistors

A one-dimensional theory of laser annealed polycrystalline silicon thin-film transistors operating in the inverted enhancement mode is described. The conductance versus gate voltage relations are characterized by two electronic parameters,namely, the charge transferred at zero-gate voltage and the interface state density. In addition to the determination of these parameter values for three actual devices of different doping levels, this analysis also reveals the roles of each parameter and suggests optimal values of these parameters for devices.

ChemInform Abstract: ELECTRICAL PROPERTIES OF THERMALLY AND LASER ANNEALED POLYCRYSTALLINE SILICON FILMS HEAVILY DOPED WITH ARSENIC AND PHOSPHORUS

Chemischer InformationsdienstVolume 13, Issue 50 Physical Inorganic Chemistry ChemInform Abstract: ELECTRICAL PROPERTIES OF THERMALLY AND LASER ANNEALED POLYCRYSTALLINE SILICON FILMS HEAVILY DOPED WITH ARSENIC AND PHOSPHORUS S. SOLMI, S. SOLMISearch for more papers by this authorM. SEVERI, M. SEVERISearch for more papers by this authorR. ANGELUCCI, R. ANGELUCCISearch for more papers by this authorL. BALDI, L. BALDISearch for more papers by this authorR. BILENCHI, R. BILENCHISearch for more papers by this author S. SOLMI, S. SOLMISearch for more papers by this authorM. SEVERI, M. SEVERISearch for more papers by this authorR. ANGELUCCI, R. ANGELUCCISearch for more papers by this authorL. BALDI, L. BALDISearch for more papers by this authorR. BILENCHI, R. BILENCHISearch for more papers by this author First published: December 14, 1982 https://doi.org/10.1002/chin.198250012Read the full textAboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat No abstract is available for this article. Volume13, Issue50December 14, 1982 RelatedInformation

Electrical Properties of Thermally and Laser Annealed Polycrystalline Silicon Films Heavily Doped with Arsenic and Phosphorus

This paper presents the results of an extensive experimental investigation on the electrical properties of heavily As‐ and P‐doped polycrystalline silicon (poly‐Si) films thermally or CW‐laser annealed. The minimum resistivity values achievable with different annealing treatments are discussed in terms of grain size, carrier concentration, and electron mobility. After thermal annealing, the As‐doped films (0.44 μm thick) have a minimum sheet resistivity of 30 Ω/sq compared to 12 Ω/sq in similarly P‐doped samples. This is due to both carrier concentration and electron mobility being lower in As‐doped samples. Mobility values of 18 and 31 cm2/V·sec are achieved in As‐ and P‐doped poly‐Si films, respectively, for the highest carrier concentrations obtainable by thermal treatments. With measurements on heavily doped single crystal silicon we have found that the ionized impurity scattering depends on the nature of the ion and is stronger for As. Moreover, the grain boundary scattering is anomalously high in thermally annealed, As‐doped poly‐Si films. Laser annealing greatly reduces grain boundary scattering in As‐doped films also without a significant increase of grain size. On the contrary, in poly‐Si films doped with P to its solid‐solubility limit ( at 1050°C) CW‐laser annealing is not essential to obtain mobility values near to those of single crystal silicon.

Electrical properties and grain size of phosphorus i n s i t u doped and cw laser annealed polycrystalline silicon films

cw laser annealing is performed on phosphorus in situ doped polycrystalline silicon films prepared for a silicon gate technology. Electrical properties and grain size of laser annealed polysilicon films are investigated for different laser power and scan rate conditions using Hall measurements and transmission electron microscopy. Depending on laser power and scan rate used, the mean grain size of polysilicon films is increased by recrystallization in either a solid phase regime (SPR) or a liquid phase regime (LPR). A previous thermal annealing step is necessary in order to obtain controllable liquid phase recrystallization. Sheet resistance reduction, due to the electrical activation of phosphorus atoms and an increase of mobility, is more important in LPR than in SPR. Indeed, desegregation of phosphorus atoms is completed as well in both regimes while effective mobility approaches single crystal value in LPR only. A carrier-trapping model shows that improvement in mobility is directly governed by the increase of mean grain size in polysilicon films. For the doping levels encountered in our films, the mean grain size sufficient to approach single crystal mobility is obtained only in LPR.

The field effect electron mobility of laser-annealed polycrystalline silicon MOSFETs

Measured I d - V d results on MOSFET's and C– V results on MOS capacitors which were fabricated on laser annealed polycrystalline silicon are presented. A scanned CW Ar + laser was used to anneal the samples. Laser power varied from 10 to 15 W in increments of 1 W; beam diameter was about 40 μ m and scan rate was about 12.5 cm/s. The field effect mobility, determined from I d - V d measurements, increases with increasing laser power. The effects of electron trapping in the polycrystalline silicon substrate were used to explain the observed mobility of the MOSFET's. In transistors annealed at low power (< 12 W), an intercrystalline potential barrier resulting from the electron trapping at crystallite and grain boundary regions was found to be the dominant factor in the channel electron conduction. Transistors annealed at high power (≥ 12 W) have fewer defect states and the intercrystalline barrier is dominant only in the low gate voltage region. In the high gate voltage region, surface structure imperfections, which cause scattering, limit the channel conduction.