Analog Signal Processing Applications Research Articles

A 0.5-V Four-Stage Amplifier Using Cross-Feedforward Positive Feedback Frequency Compensation

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 nV/Hz @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 ((µV/Hz)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.

Design of a 0.5 V Chopper-Stabilized Differential Difference Amplifier for Analog Signal Processing Applications.

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth.

CNTFET Based Fully Differential First Order All Pass Filter

A novel, carbon nanotube field effect transistor (CNTFET) based fully differential first order all pass filter (FDFAPF) circuit configuration is presented. The FDFAPF uses CNTFET based negative transconductors (NTs) and positive transconductors (PTs) in its realization. The proposed circuit topology employs two PTs, two NTs, two resistors and one capacitor. All the passive components of the realized topology are grounded. Active only fully differential first order all pass filter (AO-FDFAPF) topology is also derived from the proposed FDFAPF. The electronic tunability of the AO-FDFAPF is obtained by controlling the employed CNTFET based varactor. A tunabilty of pole frequency in the range of 10.5 to 26 GHz is obtained. Both the circuits are potential candidates for high frequency fully differential analog signal processing applications. As compared to prior state-of-the-art works, both the realized topologies have achieved highest pole frequency and lowest power dissipation. Moreover, they utilize compact circuit structures and suitable for low voltage applications. Moreover, both topologies work equally well in the deep submicron. The proposed filters are analyzed and verified through HPSPICE simulations by utilizing Stanford CNTFET model at 16 nm technology node. It is observed that the proposed circuit simulation outcomes verify the theory.

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

Electronically tunable mixed mode universal filter employing grounded capacitors utilizing highly versatile VD-DVCC

PurposeThis paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM).Design/methodology/approachThe proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V.FindingsThe proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings.Originality/valueThe proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.

Design and Implementation of CCTA for Low Power Applications: A Review

Background: Researchers have proposed a number of basic building blocks for various electronics applications. The current conveyor trans-conductance amplifier is one of them, which is suitable for linear as well as nonlinear applications of current and voltage mode circuits. Objective: This paper provides a review of the implementations proposed to date for the same with its applications in analog signal processing. The proposed possible applications of this device are also considered. Methods: Keeping in mind the utility of CCTA in low power VLSI application areas, a number of parameters like power consumption, operating voltage, 3dB bandwidth, trans-conductance, as well as a number of transistors used for implementation and technology are taken into consideration. Results: The results available for all the structures are compared and analyzed to investigate the potential advantages as well as disadvantages of this CCTA block and its limitations. Conclusion: This review concluded with a remark on the best suitable CCTA structure for low power applications and its future possibilities to use.

A new VCII based grounded positive/negative capacitance multiplier

Capacitive multipliers have found wide applications in capacitive interfaces and other analog circuits requiring large value capacitors. Recently a new active building block (ABB) called second generation voltage conveyor (VCII) has been proved to be useful in many analog signal processing applications. Due to the interesting features offered by VCII, in this paper a new VCII based implementation of grounded capacitance multiplier is proposed employing two VCIIs, two resistors and one grounded capacitor. The circuit can produce both positive and negative multiplication factors in a range of −50 to +50. Its main features are wide frequency range, high resolution, low series resistance, simple structure, low power consumption and maximum percentage error of 7.8%. The circuit enjoys high frequency range up to 10 MHz, even if it employs a floating capacitor in its structure. The behavior of the proposed circuit is analysed by taking into account also the effects of VCII parasitic elements and non-ideal gains. SPICE simulation results using a 0.35 µm CMOS technology parameters are reported. The proposed circuit has been also experimentally tested by using AD844 as VCII. Measurement results on the standalone capacitance multiplier have shown a mean percentage error of 9% across the entire gain range. Finally, the application of the proposed circuit in realizing a low pass filter is also presented to demonstrate the proposed circuit feasibility.

A linear group delay filter with tunable positive slope for analog signal processing

SummaryThis article describes the design of a tunable positive slope linear group delay filter dedicated to analog signal processing applications. The designed filter is composed of eight second‐order all‐pass cells which have been optimized to obtain a highly linear global group delay characteristic over a specified bandwidth for a specified dispersion. Each of these second‐order cells is designed with a dedicated Gm‐C topology to fit the ideal group delay characteristic with a high efficiency. Based on the sensitivity analysis of the topology, the possibility of tuning the group delay slope is highlighted. The design has been achieved with the ST CMOS 55 nm technology and has a maximum bandwidth of 2.5 GHz, a maximum reachable delay of 5.12 ns, and a group delay maximum variation of 2.5 ns. The positive slope of the group delay can be tuned in the range from 1.48 ns/GHz up to 2.03 ns/GHz. The concept of slope tunability is validated through post‐layout statistical analysis.

A Novel FSK Generator Using a Second Generation Current Controlled Conveyor

Objective: The interest concern towards the development of enabling technology towards new current mode devices has forced the designers and researchers for the invention of devices, which has having the characteristics like such as low power, robustness, compactness, efficiency and scalability. Methods: Second Generation Current Controlled Conveyor (CCCII) is the prevailing current mode device of the times today. Since its invention by A. Fabre, it has prominent applications in the field of analog signal processing and in biomedical applications too. In this manuscript, CCCII is used as an enabling device to design a Frequency Shift Keying (FSK) Generator. Results: The proposed topology is designed using a single active device CCCII with least passive components. The circuit enjoys the features of like electronic tunability of frequency using the bias current. Conclusion: It can be concluded that the FSK generator circuit designed using single CCCII confers better results in contrast to the existing structures. The maximum power consumption is 0.196 mW. The proposed circuit has the benefit of simple configuration, which is very much proficient for IC fabrication.

Designing Mixed-Signal Programmable Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies

A digitally programmable analog Fuzzy Logic Controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimization of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: a 2.7% RMSE, from 2.22 to 5.26 Mflips (Mega fuzzy logic inferences per second) at the pin terminals (@CL=13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL≤ 5pF) up to 8 Mflips may be expected.

S-band delay lines in suspended lithium niobate

Thin-film lithium niobate is an attractive platform for GHz-frequency applications in low-power RF analog signal processing, optomechanics, and quantum devices due to its high coupling, low loss, excellent optical properties, and compatibility with superconducting quantum circuits. We demonstrate aluminum interdigitated transducers (IDTs) in this platform for horizontal shear (SH) waves between 1.2 and 3.3 GHz and longitudinal waves between 2.1 and 5.4 GHz. For the SH waves, we measure a piezoelectric coupling coefficient of 13% and 6.0 dB/mm propagation losses in delay lines up to 1.2 mm with a 300 ns delay in air at room temperature. In these high keff2 transducers, electrical loading gives rise to large reflections and resonances. Finite element method models and an experimental finger-pair sweep are used to characterize the role of resonance in these transducers, illuminating the physics behind the large motional admittances of these small-footprint IDTs.

Design of integrated all‐pass filters with linear group delay for analog signal processing applications

SummaryThis article describes the design of integrated linear group delay filters for analog signal processing (ASP) applications and their implementation through constant‐resistance lattice and bridged‐T networks. Unlike previously published works, our design method uses a recursive procedure as the basis for the synthesis of a suitable transfer function. Thanks to this method, filters with a more linear group delay characteristic and flat magnitude response can be obtained. Two filters are designed in a 0.13‐μm BiCMOS technology to demonstrate the method: a balanced lattice with a negative slope and an unbalanced bridged‐T of positive slope.

Dispersive Delay Structure Based on Interdigital Capacitors With Noncommensurate Fingers

Interdigital capacitors are key components in many RF and microwave designs such as oscillators, filters, and dispersive delay structures (DDSs). A conventional interdigital capacitor has equal length fingers and has a straight shaped figure. In this letter, we introduce an interdigital capacitor with noncommensurate fingers with a curved shape and propose a modified approach for analyzing this kind of capacitors based on N noncommensurate coupled-lines network. Moreover, this capacitor is used as unit cells to create a novel DDS for analog signal processing (ASP) applications. The proposed DDS creates extremely high group delay difference of 30 ns between 1.25 and 1.75 GHz and has a compact size of $0.6 \times 0.6 \lambda ^{\mathbf {2}}$ and low insertion loss.

Experimental demonstration of active phasers based on codirectional coupling for real‐time analog signal processing

AbstractA phaser based on codirectional coupling is proposed and experimentally investigated to achieve a flat transmission magnitude while maintaining strong frequency‐dependent group delay response. This is the first experimental demonstration of such devices for real‐time radio analog signal processing applications, which are readily scalable to mm‐wave frequencies. While shielding improved the transmission performance by mitigating the radiation, a gain element is introduced to achieve a perfectly flat transmission magnitude response. The proposed structure thus forms the fundamental building block of engineering more complex dispersion profiles without compromising transmission magnitude response.

Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier

Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

A new current-mode computational analog block free from the body-effect

In this paper, a new computational/configurable analog block (CAB) is presented based on MOS translinear (MTL) for current-mode nonlinear computation. The proposed CAB architecture consists of three main structures: a new MTL cell, NMOS-PMOS arrays, and two local switch networks. As the new trait, it benefits from an effective compensation technique that extensively minimizes the error generated by body effect–the most important factor amongst the second-order effects. The second feature is that the MTL cell only with six transistors has enabled the CAB to implement more arithmetic functions. This block is capable of implementing such various nonlinear functions as squaring, inverse function, N-dimensional vector summation, full-wave rectifier, four-quadrant multiplier/divider, two-quadrant square-root, and exponential functions. The proposed CAB is simulated with CADENCE and HSPICE software in 0.18 μm TSMC CMOS technology at 1.8 V supply voltage. Most importantly, Post-layout plus Monte Carlo, corner case, and temperature variation simulations are performed to investigate its robust performance in the presence of PVT fabrication non-idealities. Functionality and flexibility of the proposed CAB make it suitable for the core block of Field-Programmable Analog Array (FPAA) ICs and signal processing applications.

Carbon Nanotubes-Based Digitally Programmable Current Follower

The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

Flexible frequency selective passive circuits based on memristor and capacitor

Abstract In analog electronic communication and signal processing applications, programmable analog filters are desirable to reduce the hardware requirement. Memristor is two states configurable nonvolatile resistor, which is small size, low power, and fast switching device. To achieve tunable cut-off frequency and bandwidth, flexible memristor-capacitor (MC) circuits are proposed, which can be applied as low pass, high pass, and band pass filters. They can be fabricated on a flexible polyethylene terephthalate (PET) substrate through electrohydrodynamic (EHD) technique. In the proposed filters, two cut-off frequencies are selected through switching two resistive states of the memristor either in high resistance state (HRS) or low resistance state (LRS), whereas the capacitor has a fixed value. The memristor is composed of graphene quantum dots (GQDs)/poly 4-vinlyphenol (PVP) composite to achieve highly stable and linear behavior and the dielectric layer of capacitor is consisted of graphene/PVP composite. The fabricated MC filters are electrically and mechanically characterized, which are matched quite well with theoretical results. From these results, it can be a good basis for tunable analog filters in wearable electronics.

Loss-Gain Equalized Reconfigurable C-Section Analog Signal Processor

We present a loss-gain equalized reconfigurable phaser for dynamic radio analog signal processing (R-ASP). Such a phaser provides real-time tunable group delay response with all-pass transmission. We propose a lumped loss-gain implementation, where tuning and equalization are mostly easily achieved. A theoretical study derives the transfer function and the fundamental characteristics of the device. The phaser is finally experimentally demonstrated, first using a single loss-gain pair and finally a three cascaded loss-gain pair structure with full reconfigurability , where up-chirp and down-chirp group delays are shown for illustration. It is expected that this phaser will find wide applications in radio analog signal processing (R-ASP) systems requiring dynamic adaptability.

A Novel All-Pass Network Implementation for Improved Group Delay Performance

In this letter, a novel all-pass network implementation is proposed using both distributed and lumped elements for high group delay. The implementation has reduced footprint and sensitivity of the group delay performance to the specified component value tolerances. It has been experimentally verified and the measured group delay is 2.4 ns at 1.85 GHz, which is thrice that reported in other approaches. The circuit finds varied applications in high resolution analog signal processing.