Abstract
Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.
Highlights
Over the last few decades, the electronics industries have seen remarkable growth in integrated circuits applications.ere is substantial increase in integration density, speed, and performance, which results in high-speed portable devices and such demands are still raising in day-to-day life
carbon nanotube field effect transistors (CNFETs) are the transistors in which number of carbon nanotubes (CNTs) acts as a physical channel between source and drain unlike virtual channel in case of metal oxide semiconductor field effect transistor (MOSFET) [8]
Top-gated undoped semiconducting MOSs like CNFETs with 4 nm thick HfO2, high-k dielectric (k 16), chirality (19, 0), and fixed diameter at 1.49 nm are used. e number of tubes is calculated using Equation (1) for pitch equals to 8 nm, keeping the diameter constant, and is itemized in Table 1. e designed folded cascode op-amp configuration is further simulated using HSPICE to achieve satisfactory DC performance and further used to calculate various performance metrics such as DC gain (Av0), phase margin (PM), unity gain bandwidth (UGB), common mode rejection ratio (CMRR), power supply rejection ratio (PSRR), slew rate (SR), output swing (OS), and power consumption [6]
Summary
Over the last few decades, the electronics industries have seen remarkable growth in integrated circuits applications. Carbon nanotube field-effect transistor (CNFET) is the competitor transistor which will permit for both the scaling process to sustain and for the progress of novel devices [4]. Ere is a significant degradation in the performance of op-amp in nanometer regime and there is a stringent requirement to reconnoitre new circuit design strategies for new upcoming devices like CNFET for their speedy merchandise to prolong Moore’s law in deep nanometer regime [6].
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