Analog Multiplexer Research Articles

Rapid cryogenic characterization of 1,024 integrated silicon quantum dot devices

As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots can potentially address these challenges given their control fidelities and potential for compatibility with large-scale integration. Here we report the integration of 1,024 independent silicon quantum dot devices with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, allowing characteristic data across the quantum dot array to be acquired and analysed in under 10 min. This is achieved by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, characterized by a typical signal-to-noise voltage ratio in excess of 75 for an integration time of 3.18 μs. We extract key quantum dot parameters by automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room-temperature transistor behaviour that could be used as a proxy for in-line process monitoring.

A 32-channels analog multiplexer with crosstalk compensation technique in 45 nm CMOS

This paper presents a multiplexer that is capable of modulating 32-channels analog signal, which is a promising approach to simplify transmission system. An 8-channels prototype multiplexer with integral functionality and non-ideal factors is fabricated in 45 nm CMOS with area of 0.59 mm2, and verified in a QAM-256 system with 1.2V supply. The proposed multiplexer employs a semi-tree structure to achieve compromise between scale and speed. To relieve adverse effect caused by crosstalk between channels, the auxiliary reset compensation circuit combined with a dedicated timing sequence is utilized. Additionally, the proposed high-speed gate voltage bootstrap switch and high-bandwidth input buffer ensure that the signal remains linear during transmission. In the experimental result, the multiplexer can achieve a pulse width of at least 77ps in 8Gbps code rate, and the root mean square error due to nonlinearity between differential input and output is 1.869 %. The error vector magnitude (EVM) obtained by analyzing output versus input of multiplexer is less than 1.413 %.

Digitally Controllable Multifrequency Impedance Emulator for Bioimpedance Hardware Validation

ABSTRACTThe accurate emulation of the electrical impedance of biological tissues is crucial for the development and validation of bioimpedance measurement devices and algorithms. This paper describes a digitally controllable impedance emulator capable of reproducing values representative of tissue bioimpedance in user‐specified resistance, reactance, and frequency ranges up to 1 MHz. The presented solution uses a 2R‐1C impedance model to emulate the impedance characteristics of a biological tissue. Specific selection of each element value in this model is achieved using analog multiplexers with low resistance. A MATLAB algorithm was developed for value estimation using target impedance requirements. An example design to emulate impedance from 1 kHz to 1 MHz with 10 to 400 resistance and maximum reactance is provided. The nonideal behavior of this design was evaluated and compared against experimentally collected impedance measurements. Deviations of <1% were observed between experimental and theoretical resistances for values up to 100 kHz (with approximately 5% deviations up to 1 MHz) and reactance deviations were also <1% up to 10 kHz. High frequency deviations are attributed to the parasitic capacitance in the realization of the design. The experimental results validate the design approach and realization for low frequencies. Overall, the innovation of the proposed approach is the control of both resistance and reactance for emulating electrical impedance representative of biological tissues.

WITHDRAWN: A 32-channels analog multiplexer with crosstalk compensation technique in 45nm CMOS

This paper presents a multiplexer that is capable of modulating 32-channels analog signal, which is a promising approach to simplify transmission system. An 8-channels prototype multiplexer with integral functionality and non-ideal factors is fabricated in 45 nm CMOS with area of 0.59 mm2, and verified in a QAM-256 system with 1.2V supply. The proposed multiplexer employs a semi-tree structure to achieve compromise between scale and speed. To relieve adverse effect caused by crosstalk between channels, the auxiliary reset compensation circuit combined with a dedicated timing sequence is utilized. Additionally, the proposed high-speed gate voltage bootstrap switch and high-bandwidth input buffer ensure that the signal remains linear during transmission. In the experimental result, the multiplexer can achieve a pulse width of at least 77ps in 8Gbps code rate, and the root mean square error due to nonlinearity between differential input and output is 1.869 %. The error vector magnitude (EVM) obtained by analyzing output versus input of multiplexer is less than 1.413 %.

Analog multiplexing of a laser clock and computational photon counting for fast fluorescence lifetime imaging microscopy.

The dynamic range and fluctuations of fluorescence intensities and lifetimes in biological samples are large, demanding fast, precise, and versatile techniques. Among the high-speed fluorescence lifetime imaging microscopy (FLIM) techniques, directly sampling the output of analog single-photon detectors at GHz rates combined with computational photon counting can handle a larger range of photon rates. Traditionally, the laser clock is not sampled explicitly in fast FLIM; rather the detection is synchronized to the laser clock so that the excitation pulse train can be inferred from the cumulative photon statistics of several pixels. This has two disadvantages for sparse or weakly fluorescent samples: inconsistencies in inferring the laser clock within a frame and inaccuracies in aligning the decay curves from different frames for averaging. The data throughput is also very inefficient in systems with repetition rates much larger than the fluorescence lifetime due to significant silent regions where no photons are expected. We present a method for registering the photon arrival times to the excitation using time-domain multiplexing for fast FLIM. The laser clock is multiplexed with photocurrents into the silent region. Our technique does not add to the existing data bottleneck, has the sub-nanosecond dead time of computational photon counting based fast FLIM, works with various detectors, lasers, and electronics, and eliminates the errors in lifetime estimation in photon-starved conditions. We demonstrate this concept on two multiphoton setups of different laser repetition rates for single and multichannel FLIM multiplexed into a single digitizer channel for real-time imaging of biological samples.

Система для экспериментальной оценки паразитных параметров интегральных мультиплексоров для электроимпедансной томографии

Physical parameters of analog multiplexer have influence on measuring, provided for electrical impedance tomography. For bio-medical application the most important is channel stray capacitance and difference among channels. Typical value is around several tens of picofarads. Integrated circuit manufactures usually do not specify this parameter and provide only typical value. Actual stray capacitance can be different from batch to batch up to several tens percentage. Parameter testing and selection can provide better quality of measurement or help to decrease influence of capacitance differences between channels. Leakage currents can cause significant influence on measurements. Especially, multiplexers lightly damaged by static electricity, can increase their leakage currents by an order of magnitude. Software and hardware system for testing of the multiplexers was developed. It can test main parameters of high voltage precision analog multiplexer, like: channels commutation, charge injection during channel switching, channels resistance, capacitance and leakage currents. Channel capacitance measurement accuracy is better than 1 pF, indeed we should substitute stray capacitance of reference multiplexer and empty test-socket. Channel capacitance measurement accuracy is around 1 Ohm, charge injection is around 1 pQ, leakage current around 100 pA. For testing we use reference multiplexer with known parameters, timer to measure charge-discharge time for capacitance estimation, precision amplifier and reed switch to measure small voltage. Replaceable sockets help test analog multiplexer not only 1 to 16 configurations, but any other configuration with smaller number of channels and even lower voltage supply if use voltage stabilizer embedded in the socket. System can check that multiplexer is fine, choose the same parameters of ICs for existing system, improve quality by choosing the ICs with the best parameters or measure them for further compensation by software.

Radiation tolerance of the MUX64 for the High Granularity Timing Detector of ATLAS

The MUX64 ASIC is a 64-to-1 analog multiplexer to accommodate 64 inputs, with one addressed to output for ADC readout. It is developed for monitoring of the Low-Gain Avalanche Detectors (LGAD) detector modules in the High Granularity Timing Detector (HGTD) of the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb-1. This work presents the radiation tolerance study for the MUX64 being tested with 80 MeV protons and X-ray exposures for damages caused by Non-Ionizing Energy Loss (NIEL) and Total Ionizing Dose (TID), respectively. The irradiated samples demonstrated tolerance to the NIEL to a fluence of 3.21 × 1015 (Si, 1 MeV) neq/cm2, and the TID of 7.46 × 105 Gy (Si).

Modelling and design of asynchronous receptive circuit for cone pathways

In this paper, asynchronous receptive circuit of retinal pathway is proposed for cone cells. Cone cells respond differently to different wavelengths of light and they are responsible for color vision. The cells present in retinal pathway namely cone photoreceptor, bipolar cell, amacrine cell and ganglion cell are mimicked using 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology in strong inversion region. The proposed circuit is event based and hence asynchronous in nature. Additionally, amacrine stage is mimicked such that analog multiplexing occurs which is matching with its biological behavior. Both these features give output near to response of actual biological retinal pathway. The circuit detects wavelengths in visible spectrum of light with temporal contrast. At amacrine stage, selectivity is achieved without any external control signal which shows intelligent behavior at analog circuit level. The concept of color sensitivity of cone is considered to generate input stimulus of the circuit using Commission on Illumination (CIE) standard. The power consumed by the entire pathway circuit is 183 mW.

Reversible multiplexing analog and digital optical information storage in Eu3+ doped perovskite-type photochromic materials

Photochromic materials have received increasing interest benefited by its promising application in anti-counterfeiting and erasable optical information storage with the rapid development of the information age. In this work, we have reported a perovskite configuration SrHfO3:Eu3+ photochromic powders, displaying the color changed from white to brown upon UV light irradiation, and it can be bleached by 365 nm light or heat treatment. Based on the energy transfer, the Eu3+ ions doped into SrHfO3 host to obtain luminescence modulation attribute to the special excitation (302 and 396 nm) and emission (614 nm) properties, and the more efficient luminescence modulation is excited at 396 nm. The storage of verbal, images and digital signal can be realized by UV light irradiation, then the stored information can be read out through 254 nm light, and the recording information can be erased using 365 nm light illumination. In addition, the anti-counterfeiting application has achieved by employing alternating UV and 365 nm light illumination. Furthermore, the stored information undergoes several cycles with almost no degradation of “written in”, “read out” and “erased”, displaying excellent fatigue resistance and reversibility. These results suggest that the perovskite configuration SrHfO3:Eu3+ photochromic material has promising multi-functional application in optical information storage and anti-counterfeiting.

A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology

Despite the scaling of the supply voltage of deep-submicrometer CMOS technologies, many applications still require to deal with off-chip signals in high-voltage domains (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5~ \mathrm{V})$</tex-math> </inline-formula> . Hence, foundries offer fabrication processes with voltage-tolerant transistors, which are inherently protected from the electrical stress, at the expenses of compromising their performances, reducing the design portability, and augmenting the production costs in case of the customization of the process. As an alternative, circuit techniques, such as cascoding, adaptive biasing, and voltage shifting, result effective in designing analog circuits, such as amplifiers and voltage drivers at high supply voltage with voltage-scaled transistors. This article presents the architecture of a switch for analog multiplexers (MUXs) able to handle signals up to twice the nominal supply voltage of the employed transistors. To validate the circuit choice, a switch for a 5-V MUX has been designed with 2.5-V transistors in 28-nm CMOS technology. The comparison with a benchmark architecture with tailored 5-V devices shows that an about three times larger area and 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A static current demand have to be considered. Moreover, an accelerated degradation test (ADT) showed a similar decay of the features of both types of switches.

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS high granularity timing detector

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 °C shows negligible degradation over 16 days.

End-to-End Real-Time Service Provisioning Over a SDN-Controllable Analog mmWave Fiber -Wireless 5G X-Haul Network

The current work presents the first experimental demonstration of real-time Ethernet (ETH) trial services and 4K-Ultra High Definition (UHD) video application transmission over a 2λ Wavelength Division Multiplexing (WDM) analog Fiber-Wireless (FiWi) mmWave X-haul network, supporting dynamic flexible capacity allocation through an integrated silicon photonic Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> Reconfigurable Optical Add Drop Multiplexer (ROADM) and 60 GHz wireless transmission across a 7 m V-band link distance, while controlled by a Software Defined Network (SDN) controller based on Open Daylight. Analog X-haul transport of the radio signals is based on an Intermediate Frequency over Fiber (IFoF) scheme centered at 1.5 GHz using an Orthogonal Frequency Division Multiplexing (OFDM) radio-waveform with a bandwidth of 204 MHz, generated by a Field Programmable Gated Array (FPGA)-based RF System-on-Chip (SoC) processor that converts on-the-fly the real-time ETH downlink traffic to analog radio and vice-versa for the uplink. Dynamic allocation of the X-haul traffic capacity is handled through the use of the 802.1Q Virtual Local Area Network (VLAN) tag-mechanism, which controls the forwarding operation to the proper DAC and InP EML for optical modulation using Intensity Modulation/Direct Detection (IM/DD) schemes, while the wavelength routing operation is handled by the low-loss four-port Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ROADM featuring only 2.5 dB fiber-to-fiber losses based on a cascaded MZI-interleaver design on the TriPleX platform, routing the real-time traffic to a second mmWave antenna site. Detailed measurements and traffic statistics indicate end-to-end latency of less than 260 μs and a packet loss less than 0.0054% across a dynamic range of at least 6.5 dB in the optical domain, while the high user bandwidth and signal quality are validated by an uninterrupted 4K-UHD video transmission across the FiWi X-haul mmWave transport network. The current work aims to shape a complete technology roadmap for Point-to-Multipoint FiWi transport network architectures with high spectral efficiency X-haul transport for dense areas and 5G/6G hotspots of future mmWave Centralized Radio Access Networks (C-RANs).

Bandwidth Tripler: Broadband Signal Generation With an Image-Rejection Analog Multiplexer for Fiber Optic Transmitters

This article describes a frequency-interleaved digital-to-analog conversion technique named bandwidth tripler with an image-rejection analog multiplexer (AMUX). The tripler extends the bandwidth of the parallelized sub-digital-to-analog converters (DACs) by three times in the frequency domain. Image rejection using the phase-shifted method reduces analog filters for combining divided sub-bands, which improves the signal quality and size of the analog circuits. Besides, the tripler outputs no spurious signals out of the target bandwidth. The AMUX for the tripler was fabricated in 180-nm CMOS technology. Pseudo-differential switches were used to reduce distortion, and a broadband termination circuit was inserted at the output of the AMUX to compensate for the limited performance of the CMOS devices. The fabricated AMUX was evaluated by S-parameter and time-domain measurements. The S-parameter measurement results demonstrated a bandwidth of 23.4 GHz. In addition, broadband signal generation for 30 Gbps PAM4 was demonstrated without using any equalization. The power consumption of the AMUX was only 49 mW. This high-speed performance is comparable to the conventional DACs fabricated using advanced CMOS processes.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

Bidirectional WDM Multi-Nodes Analog Radio-Over-Fiber Mobile Fronthaul Link Enhanced by Photonic Integrated Devices

A bidirectional wavelength division multiplexing (WDM) analog radio-over-fiber (A-RoF) mobile fronthaul (MFH) link is enhanced using photonic integrated devices. Two key photonic integrated devices are combined in the A-RoF link: an 8-channel InP directly modulated laser (DML) transmitter and a 32×100-GHz silicon array waveguide grating (AWG). The DML transmitter has 8 parallel monolithically integrated distributed feedback lasers, enabling cooperative and reconfigurable downlink analog transmission. Moreover, the 32×100-GHz AWG is featured by low insertion loss (<4.5-dB) and low crosstalk (<−20.4-dB), to achieve a high-density WDM system. In the distributed field experiments, we have successfully demonstrated a bidirectional A-RoF MFH over 10-km standard single mode fiber, providing an 8×5-Gbit/s 4-quadrature amplitude modulation (QAM) orthogonal frequency division modulation (OFDM) downlink transmission and a 3×12-Gbit/s 16-QAM uplink transmission.

A Novel Segmented LDMOS-SCR Structure With 8-kV HBM ESD Robustness in CMOS Analog Multiplexer

A novel segmented laterally diffused MOS embedded silicon-controlled rectifier (SCR) structure, called NSLDMOS-SCR, is proposed and verified in an optimal 5-V/40-V bipolar CMOS DMOS (BCD) process. Superior to the strip LDMOS-SCR, the proposed NSLDMOS-SCR exhibits a high holding voltage of 20.6 V and an excellent failure current of 12.2 A in a width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$200~\mu \text{m}$ </tex-math></inline-formula> , benefitting from the widened segmented topology of the source and body. As such, for ±15-V circuit application, the NSLDMOS-SCR can fit the electrostatic discharge (ESD) design window for an eight-channel CMOS analog multiplexer and effectively protect these pins against 8-kV human-body-mode ESD stress.

Speed-Power Improvement in High-Voltage Switches Employed in Multielectrode Arrays

In multi-electrode arrays (MEAs), for electrical recording and electrical stimulation, high voltage (HV) switches are employed to build an analog multiplexer to conduct either a HV stimulation signal from the pulse generator circuit to an electrode or a low-voltage noise-sensitive signal from the electrode to a recording stage. In this brief, a new circuit structure is proposed for HV switches that significantly improves their switching speed, reduces their power dissipation, and also employs a minimum number of bulky HV devices. In order to reduce the transition time of the proposed switch without consuming a large amount of power, during the transition time that the switch is turning on/off, a large current flows through the driver circuit of the switch to turn the switch on/off rapidly; however, after the transition times, this current is significantly reduced to save power. Based on the proposed HV switch, a multiplexer structure has been implemented in 25-V, 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS IC technology and the measurement results prove its efficacy. Supplied with 25 V and operating with 300 nA current consumption, this switch swings over 20 V with a relatively constant on-resistance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100 \Omega $ </tex-math></inline-formula> and features a 80 ns transition time.

A simple chaotic base encryption scheme for securing OFDM-PON communications

Abstract Optical communications and their security have been got a great attention. In this work, a simple, low cost and secure optical system integrating orthogonal frequency division multiplexing-based passive optical network (OFDM-PON) and chaotic theory is proposed. In the proposed system, a novel scheme of quadrature amplitude modulation (QAM) encryption method is adopted. For privacy of image and video encryption, the process of encryption consists of two processes and a 3D chaotic system is employed. The chaotic system is used to generate the encryption sequences. In the first stage, the first generated chaotic sequence is XORed with the incoming data. While in the second stage, the QAM symbol is remapped using the other two generated chaotic sequences. Generally, the proposed system is designed to provide secure data, videos, and images transmission. The proposed system is simulated and evaluated with a transmission of a 10 Gb/s along 50 km single-mode fiber (SMF). The performance of the proposed system showed that there is a performance enhancement in terms of Peak to average power ratio (PAPR) and bit error rate (BER). The BER of unauthorized user is around 0.6147, while the PAPR is reduced to approximately half. The proposed system is simple and doesn’t require complex computations. It requires simple analog multiplexers for its implementation.

Multiplexed Readout for an Experiment with a Large Number of Channels Using Single-Electron Sensitivity Skipper-CCDs.

This paper presents the implementation of a multiplexed analog readout electronics system that can achieve single-electron counting using Skipper-CCDs with non-destructive readout. The proposed system allows the best performance of the sensors to be maintained, with sub-electron noise-level operation, while maintaining low-bandwidth data transfer, a minimum number of analog-to-digital converters (ADC) and low disk storage requirement with zero added multiplexing time, even for the simultaneous operation of thousands of channels. These features are possible with a combination of analog charge pile-up, sample and hold circuits and analog multiplexing. The implementation also aims to use the minimum number of components in circuits to keep compatibility with high-channel-density experiments using Skipper-CCDs for low-threshold particle detection applications. Performance details and experimental results using a sensor with 16 output stages are presented along with a review of the circuit design considerations.

A Prototype System With Custom-Designed RX ICs for Contrast-Enhanced Ultrasound Imaging

This work presents a prototype system based on a multichannel receiving (RX) integrated circuit (IC) for contrast-enhanced ultrasound (CEUS) imaging. The RX IC is implemented in a 40-nm low-voltage CMOS technology and is designed to interface to a capacitive micromachined ultrasonic transducer array. To enable a direct connection of the RX electronics to the transducer, an analog multiplexer with on-chip protection circuitry is developed. Stress tests confirm the reliability of this arrangement when combined with a high-voltage pulser. The RX IC is equipped with a highly programmable bandpass filter to capture harmonic signals from ultrasound contrast agents (UCAs) while suppressing fundamental components. In order to examine the impact of analog front-end (AFE) bandpass filtering, in vitro acoustic experiments are performed with UCAs. A spatial resolution analysis suggests that the AFE bandpass filtering combined with a pulse inversion (PI) technique can improve the lateral resolution by 38% or 9% compared to the original full-bandwidth approach or a stand-alone PI approach, respectively, while the impact on axial resolution is negligible. A phantom study shows that compared to digital bandpass filtering, the AFE bandpass filtering enables better use of the dynamic range of the RX electronics, resulting in better generalized contrast-to-noise ratio from 0.44/0.53 to 0.57/0.68 without or with PI.