Performance Of Analog-to-digital Converter Research Articles

Quantization error for weak RF simultaneous signal estimation

In a congested signal environment, it is difficult to obtain estimates of weak RF signal parameters. Determining signal parameter estimates in real time is a challenge for electronic warfare receivers that aim to receive multiple simultaneous signals. Prior work provided estimates of weak signal parameters (weak signal frequency and weak signal amplitude) without taking into account any error introduced by analog-to-digital converters that are inherently part of digital signal processing systems. In order to obtain realistic estimates, we need to take error introduced by an ADC into account. The primary aim of this paper is to quantify error introduced by a single ideal ADC as a function of angle. This paper presents a method to estimate angle resolution and quantization levels in N-bit analog-to-digital converters (ADCs) for use in a weak radiofrequency (RF) simultaneous signal estimation process. The paper quantifies the error in the angle quantization of an N-bit ADC for an input complex signal that is the instantaneous frequency obtained for the situation in which there are two simultaneous signals (with one strong signal and one weak signal) in a weak RF simultaneous signal estimation process. The presented method describes the process to determine the angle quantization range, angle quantization uncertainty, and angle quantization error. This approach has potential applications in electronic warfare (EW) systems. The approach also has potential for assessing ADC performance for measurements that approach the quantum limit. Results are presented for 1-bit, 2-bit, 3-bit, and 10-bit ADCs.

Comparison of Low Power High Speed Comparator for Flash ADC

The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.

A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration

In high-speed pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs), the residue amplifiers dominate the overall ADC speed, power, and accuracy. To improve the ADC performance, this brief proposes a large-swing high-linearity fully-dynamic open-loop amplifier. By setting the cascode input transistors in linear region, both the input/output swing and the linearity are improved significantly. By clamping the drain voltages of input transistors, the amplifier gain is PVT insensitive. These drain voltages of input transistors are clamped through a dynamic comparator with small size, which helps save energy. The comparator offset is automatically canceled out through a novel thermal-noise-based technique. Designed in a 40nm CMOS process, the proposed amplifier achieves an output swing of 400mVpp, a settling accuracy of 8-bit ENOB, and a voltage gain of 16X, under a 100MHz clock frequency. It is fully-dynamic and only consumes 1.15mW of power under a 1.1V supply. Compared to the state-of-the-art dynamic amplifiers, the output swing is increased by 4 times; the settling accuracy is improved by 2 bits; the voltage gain is increased by 4 times; the PVT sensitivity of voltage gain is reduced by 4.7 times; and the power consumption is decreased by 45% with fully-dynamic operation.

Broadband and linearized photonic time-stretch analog-to-digital converter based on a compact dual-polarization modulator.

A broadband linearization scheme for a photonic time-stretch (PTS) analog-to-digital converter (ADC) is proposed based on a dual-polarization binary phase-shift keying (DP-BPSK) modulator with complementary parallel single-sideband (SSB) modulation. In this system, two stretched radio frequency signals, corresponding to the two orthogonal polarizations of the DP-BPSK modulator, are complementary, which can realize differential operation to eliminate the second-order harmonic distortion and pulse envelope distortion. Meanwhile, SSB modulation is used to avoid dispersion-induced power fading. Theoretical analysis and simulation results show that the proposed scheme can effectively improve the linear performance of PTS ADC, even considering the polarization-dependent delay deviation and amplitude offset.

A novel capacitor recombination calibration method applied to 18-bit SAR ADC

In this paper, a calibration method applied to Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is designed, especially applied to the capacitive array in resistive–capacitive combined SAR ADC. Conventionally, auxiliary Digital-to-Analog Converter (DAC) foreground calibration, dynamic element matching (DEM) or digital background calibration are widely used to enhance linearity of data converters. This paper proposes an off-line capacitor selection calibration method that uses an optimal sequence of unity elements for an overall improvement of Signal to Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), differential nonlinearity (DNL) and integral nonlinearity (INL). It is worth mentioning that the capacitor mismatch only needs to be calibrated after power on, this kind of foreground calibration will not increase the power consumption of ADC during the normal operation, while the background calibration will consume power consumption all the time. It is important that the calibration proposed is highly relied on a high resolution comparator. This paper provides a high resolution comparator design, the resolution of the comparator reaches 8.35 μV, which already satisfies the demand of a 18-bit differential SAR ADC. During the process of calibration, all capacitors are divided into unit capacitors, and then the capacitors are sorted, reorganized to form each bit. The calibration method is verified by simulating a 18-bit SAR ADC with 500 Monte-Carlo runs, the simulation results show that the average value of SFDR is enhanced by about 36 dB and the average value of SNDR is enhanced by about 27 dB. Therefore, the proposed method is simple and significantly improves the static and dynamic performance of the ADC without obvious additional hardware, and greatly saves area and power consumption. Finally, it is worth mentioning that in high-precision SAR ADCs design, especially above 16 bits, comparator noise and the voltage coefficient of capacitors are the main factors limiting ADC performance, which are not considered in this work.

An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration

A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 ㎟ and 248 μW, respectively.

Development and Implementation of a Low-Cost Test Solution for High-Precision ADC Chips Based on Intelligent Sensor Networks

Analog-to-digital converters (ADCs) are moving toward high speed and high resolution for low-cost testing. Based on the theory of intelligent sensor network, this paper designs a low-cost test solution for high-precision ADC chips, which solves the problems related to signal integrity. It mainly includes the following: designing an appropriate circuit connection scheme, planning an appropriate PCB stack-up structure, formulating detailed layout and wiring constraints, etc., and building a high-speed ADC test platform to obtain static and dynamic performance; based on the existing instruments in the laboratory, the effects of different signal sources, different input powers, and the presence or absence of filters on the dynamic performance of high-speed ADCs are studied. In the simulation process, the HyperLynx simulation platform is used to design and simulate the signal integrity of the high-speed acquisition board. Combined with the relevant theoretical knowledge of the signal integrity of high-speed digital circuits, the signal integrity analysis and simulation of the ADC module circuit and the DDR3 high-speed memory circuit are carried out, respectively. The results show that, taking the histogram method as a reference, when the optimal 30 windows are selected, the integral nonlinearity (INL) error of the proposed method is 0.12 LSB, the highest sampling frequency is up to 5GSps, and 61440 sampling points are required. The time is reduced by about 30% compared with the excitation error identification and removal (SEIR) method, which effectively improves the low-cost test effect of the ADC chip.

A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor-Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System.

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

In the Pursuit of the Optimal Accuracy–Speed–Power Analog-to-Digital Converter Architecture: A mathematical framework

The everlasting challenge in the design of every analog-to-digital converter (ADC) lies in maximizing the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">accuracy</i> · <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">speed</i> ÷ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">power</i> product by pushing all metrics toward their desired directions. To this end, tremendous progress has been made in advancing ADC performance both circuit- and architecture-wise. These advances have been captured by means of comparing experimental data points in surveys, with <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> being the most noteworthy. However, such comparisons give an ill-defined view since the data points correspond to different architectures that were optimized under different constraints and implemented in different process nodes. This provides little insight on architectural limits and makes a direct comparison under similar assumptions nontrivial.

A short review of some analog-to-digital converters resolution enhancement methods

The resolution of the analog-to-digital converter (ADC), i.e. the minimum voltage that ADC can recognize, is an important indicator of ADC performance. In order to improve the accuracy of ADCs, some approaches are proposed to enhance the resolution of ADC. This paper presents a review of ADC resolution enhancement schemes, which includes the introduction of primary features, the explanation of basic principles, as well as their merits, demerits, and trade-offs. It describes a variety of resolution enhancement schemes from different aspects such as signal processing, ADC calibration, and novel acquisition architectures, and analyzes their applicable scenes. Finally, some challenges and issues are briefly summarized, as well as some comments on future work in this field. By reviewing the current literature, we can make recommendations on the design of acquisition system resolution according to the actual requirements.

11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11- $\mu \text{m}$ 1P4M CIS process with a 2.9- $\mu \text{m}$ pixel pitch. A maximum frame rate of 570 frames/s was achieved with a $1024\times240$ pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 $\text{e}^{-}\cdot $ nJ and 0.41 $\text{e}^{-}\cdot $ nJ/step.

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm $$^{2}$$ area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters

Non-shaping dynamic element matching (DEM) randomization schemes are widely adopted for wideband Nyquist-rate digital-to-analog converters (DACs) within transmitter architectures. Here, randomization translates the mismatch-induced distortion into white noise from dc to $\text{F}_{\mathrm{ s}}$ /2 range. However, the DAC performance for various bands within the Nyquist range cannot be improved using non-shaped DEMs as their inherent structure cannot be made programmable. Conversely, mismatch-shaping DEMs can be made tunable to shape the DAC errors over various signal bands, which makes them suitable for wireless transmitter applications. This paper presents the design methodology for high-order mismatch-shaping DEM architectures suitable for wideband Nyquist DACs. The challenge in designing high-order DEM structures for Nyquist DACs is to make them programmable to cover various signal bands within the Nyquist range and to operate them at high-frequencies demanded by the applications. Moreover, the stability of the high-order loop-filter within the DEM and its implementation cost is of great concern. This work details techniques to design programmable, stable, and hardware efficient high-order DEM structures for wideband Nyquist DACs. The DEM structures are implemented on an UltraScale+ FPGA device for prototyping and validation. Furthermore, the DEM design operation is validated by obtaining the measurement results interfacing with a 5-bit analog DAC.

High-Precision ADC Testing With Relaxed Reference Voltage Stationarity

This article seeks to simplify the scope of on-chip built-in self-test (BIST) schemes for the static testing of analog-to-digital converters (ADCs) by relaxing the precision and constancy requirements for the reference voltage of the system. The proposed testing methodology is based on appropriate modifications to the “stimulus error identification and removal (SEIR)” algorithm (Jin et al., 2005), which already addresses the stringent linearity constraints on the input stimulus. Simulation results with the proposed algorithm are presented for a prototype 14-bit SAR ADC, wherein the nonlinearities of the input signal and the nonstationarities of the reference voltages are estimated to obtain the actual ADC performance. Once the ADC linearity is known, standard digital calibration schemes can be employed to achieve higher resolution.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

PurposeThe purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.Design/methodology/approachAn op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2.FindingsMeasured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.Originality/valueThe experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

Implementation of digital-to-analog converter through CP-based GaAs/GaSb nanowire GAA-TFET

Digital-to-analog converter (DAC) is the most critical circuit of any chip which limits system performance and consume much power. Therefore, the focus of this work is the DAC implementation using GaAs/GaSb-based charge plasma nanowire GAA-TFET which provide better ON current at reduced ambipolarity and hence, reduce power consumption. Also, the linearity of the proposed device is much better than Si TFET due to the absence of random dopant fluctuation and hence, improves DAC accuracy. The DAC implemented here is the R–2R and current steering architecture which is the first ever known work of a charge plasma-based hetero-material nanowire TFET. For the DAC implementation, Verilog A lookup table is created from the simulated results of this device from TCAD Silvaco and rest of the circuit simulation is carried out in Cadence. Finally, DAC performance metrics have been analyzed and found that efficiency of current steering has been drastically improved compared to R–2R architecture.

New digital background calibration method for pipelined ADCs

Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

A probability density estimation algorithm on multiwavelet for the high-resolution ADC

ADC (Analog-to-digital converter) is an important component in measuring instruments that converts the analog signals to digital form. The actual effective vertical resolution of ADC is one of the most important indicators for evaluating the ADC performance. However, it is restricted by various factors such as external disturbance, environmental interference, clock jitter, transmission delay, etc. These problems lead to a lower ADCs’ effective resolution than the ideal value. This paper proposes an improved algorithm dedicated to decrease errors in measured signals. In this algorithm, we make Multiwavelet decomposition to get the probability density function of measured signal first, then use singular value decomposition to remove the noise related frequency characteristic values in the multiwavelet basis coefficients, next create a Bayesian fusion iteration process to optimize the probability density function and build a confidence interval for elimination of the noise data, and finally the signal is reconstructed and average filtered for output. Through simulation experiments we show an improvement of the vertical resolution and SNR (signal-to-noise ratio) in comparison to the conventional averaging filter, high resolution acquisition and oversampling methods.