High-Precision ADC Testing With Relaxed Reference Voltage Stationarity

Abstract

This article seeks to simplify the scope of on-chip built-in self-test (BIST) schemes for the static testing of analog-to-digital converters (ADCs) by relaxing the precision and constancy requirements for the reference voltage of the system. The proposed testing methodology is based on appropriate modifications to the “stimulus error identification and removal (SEIR)” algorithm (Jin et al., 2005), which already addresses the stringent linearity constraints on the input stimulus. Simulation results with the proposed algorithm are presented for a prototype 14-bit SAR ADC, wherein the nonlinearities of the input signal and the nonstationarities of the reference voltages are estimated to obtain the actual ADC performance. Once the ADC linearity is known, standard digital calibration schemes can be employed to achieve higher resolution.