Analog-to-digital Converter Parameters Research Articles

ЗАВИСИМОСТЬ СПЕКТРАЛЬНЫХ ХАРАКТЕРИСТИК СИГМА-ДЕЛЬТА АНАЛОГО-ЦИФРОВЫХ ПРЕОБРАЗОВАТЕЛЕЙ ОТ ПОГЛОЩЕННОЙ ДОЗЫ ИОНИЗИРУЮЩЕГО ИЗЛУЧЕНИЯ

This paper presents the results of the study of sigma-delta analog-to-digital converters` main spectral parameters` dependence on the total ionizing dose (TID). Within the framework of this study the main parameters of analog-to-digital converters (ADC) (dynamic, static and electrical) were controlled. The main dynamic characteristics of sigma-delta ADC are signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), signal-to-noise and distortion ratio (SINAD) and total harmonic distortion (THD). Those have been determined from the spectrum of digitized sine signal using the fast Fourier transform (FFT). Static parameters (integrated nonlinearity (INL), offset and gain errors) were determined using a straight line that linearizes the transfer function, according to the method which is described in the IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters. National Instruments modular measuring equipment was used for testing ADC`s parameters. Comparative data on the dose dependence of static and dynamic parameters of two sigma-delta ADC and one sigma-delta modulator are obtained. Based on the results, it was concluded that the most sensitive parameters of sigma-delta ADC to TID are its dynamic parameters. Therefore, when assessing the sigma-delta ADC`s radiation hardness, the spectral characteristics of absorbed dose should be kept under control.

Effect of ADC parameters on neural network based chaotic optical communication

The performance of traditional chaotic optical communications depends on the matching parameters of the chaotic transmitter and receiver. The chaotic receiver based on the neural network (NN) can solve the dependence on matching parameters, but the analog-to-digital converter (ADC) has an effect on the decryption performance. In this paper, the effects of sampling rate and digitalizing bit for ADC on NN-based chaotic optical communication systems with different feedback strengths at different bit rates are numerically studied. The results show that the requirements for ADC will be higher if the feedback becomes stronger. In order to achieve higher speed chaotic optical communications, the ADC with higher performance is needed. These results can give guidance for the applications of NN-based high-speed chaotic optical communication systems.

Four innovative calibration algorithms for capacitive mismatch in 18‐bit redundant split SAR ADC

SummaryFour calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog‐to‐digital converter (ADC). An 18‐bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte‐Carlo runs with a standard deviation of 0.1% (σ0/C0 = 0.001). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64‐dB enhancement of spurious‐free dynamic range (SFDR) and a 3.33‐bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re‐exchanging method I (SREI) show that a 21.64‐dB enhancement of SFDR and a 3.34‐bit improvement of ENOB have achieved, respectively

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

Dynamic parameter estimation of Analog to Digital Converter with multipoint Interpolation technique

Objectives: The objective of this paper is to estimate the dynamic parameters of Analog to Digital Converter (ADC) with multi frequency sine signal as stimuli. Methods/Statistical Analysis: Traditionally the characteristics of a signal are estimated with its spectrum using Fast Fourier Transform (FFT) algorithm. Interpolated FFT technique gives more accurate results compared to the FFT technique. The signal is weighted with rectangular and Hanning window before the Discrete Fourier Transform (DFT) is calculated, frequency and magnitude of various components of input stimulus are estimated with this technique. Weighted signal is applied to ADC under test and the frequency spectrum of digital output is obtained. Findings: This technique is used to determine the frequency dependent parameters of ADC. The analytical formula for amplitude, frequency and phase estimation is simple to implement. The expression for the accurate estimation of the fractional part between the two largest spectrums of the recorded cycles by IP DFT method is presented. Sampled input signal is weighted with rectangular and tapered window and averaged. A reduction in noise level can be observed in the spectrum. The obtained values of frequency, amplitude and phase which are more accurate as presented in literature. Comparative values of ideal and real ADC dynamic parameters are presented here. The research work carried can contribute significantly to ADC design and testing with multi frequency input signals. The novelty of this approach is that the accurate results for dynamic parameters of ADC can be characterized for a particular bandwidth in a single run. Application/Improvements: An ADC is a vital component in high-speed data communications video and radar systems. The overall accuracy of the system is dependent on the accuracy of the ADC. For such systems, dynamic testing of the device using standard signal is not useful. Therefore dynamic testing of ADC under application conditions is needed. The techniques discussed in the paper are very much useful in testing high-speed ADCs by the manufacturer as well as a circuit designer. Keywords: Analog to Digital Converter, Dynamic Parameters, Multi Frequency Signal, Multipoint Interpolation

Impact of ADC parameters on linear optical sampling systems

Linear optical sampling (LOS), based on the coherent photodetection of an optical signal under test with a low repetition-rate signal originating from a pulsed local oscillator (LO), enables the characterization of the temporal electric field of optical sources. Thanks to this technique, low-speed photodetectors and analog-to-digital converters (ADCs) can be integrated in the LOS system providing a cost-effective tool for characterizing high-speed signals. However, the impact of photodetector and ADC parameters on such LOS systems has not been explored in detail so far. These parameters, including the integration time of the track-and-hold function, the effective number of bits (ENOB) of the ADC, as well as the combined limited bandwidth of the photodetector and ADC are experimentally and numerically investigated in a LOS system for the first time. More specifically, by reconstructing 10-Gbit/s non-return-to-zero on–off keying (NRZ-OOK) and 10-Gbaud NRZ-quadrature phase-shift-keying (QPSK) signals, it is shown that a short integration time provides a better recovered signal fidelity. Furthermore, an ENOB of 6 bits and an ADC bandwidth normalized to the sampling rate of 2.8 are found to be sufficient in order to reliably monitor the considered signals.

A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter

This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed.

High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, −0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

Behavioral Modeling of Typical Non-Ideal Analog to Digital Converter Using MATLAB

Analog-to-digital converters (ADC) are one the most fundamental and crucial parts of an electronic device which needs to convert analog inputs into the digital format. Nowadays, you can find some type of ADCs in almost every communication device. Consequently, simulating an ADC plays a challenging and very fundamental role while aiming to simulate real-world instruments and designed systems. Despite the fundamental significance of this task, a general simulation model for typical non-ideal ADCs have not been presented yet. In this paper, we consider the most important non-ideality parameters of a typical ADC and initiate simulation models in the Simulink environment of MATLAB, as the most versatile widely-used simulation software for engineering tasks. For this purpose, we first reconsider the non-ideality parameters of a typical ADC from general perspective, aiming to bring a unified view in hand. Afterwards, the potential models for the non-ideality parameters are initiated separately, and then, are combined together to make the whole model. By creating a MATLAB Block of the whole general-topology model at the end, and defining the non-ideality parameters as variable inputs, we simulate the behavior of a typical ADC using practical non-ideality parameters data, and compare with an ideal ADC. This additionally enables a user interface for quick input of non-ideality parameters of any practical ADC for future clients. Despite the pure generality of the model, simulation results demonstrate acceptable outcomes proving the applicability of this model in wide range of engineering simulation tasks, and an appreciable step towards higher precision general simulations of typical ADCs.

Use Spectrum Analysis to Test the Frequency-Domain Characteristics Parameters of ADCs

Many frequency-domain characteristics parameters can describe the dynamic behaviour of Analog to Digital Converters (ADCs). This paper researched how to use a sinewave stimulus and spectrum analysis to test those parameters. It analyzed the spectrum of coherent sampling and incoherent sampling of ADC response to a specified amplitude and frequency sinewave firstly. Incoherent sampling causes spectrum leakage. To reduce the errors in calculating parameters introduced by spectral leakage, this paper multiply the data record by a window function in the time domain prior to the DFT process. Simulate results demonstrate that window function can reduced the spectral leakage introduced by incoherent sampling and increase ADC parameters calculation accuracy.

LabVIEW application for computer simulation of the conversion technique of dual-slope analog-to-digital converter

The application designed in the LabVIEW environment for computer simulation of the work and simulation testing of analog-to-digital converter (ADC) with dual-slope conversion method is presented. The front panel contains graphical objects, permitting interactive communication with the user and the animation effects allow illustration of the ADC operation principle. The application permits the performance of virtual experiments thanks to the possibility of modification of the ADC parameters and the input signal parameters. The virtual electronic experiments presented in the paper simulate the real measurement processes. The application can be used for both education and specific research purposes.

Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters

In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta (CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it can be expanded using out-of band test tones for background calibration schemes.

Gain error, offset error and ENOB estimation of an A/D converter using histogram technique

This paper reports estimation of gain error, offset error and Effective Number of Bits (ENOB) of an Analog to Digital Converter (ADC) using histogram technique for sine wave as input test signal. Computation of code transition levels of ADC transfer characteristics is done by collecting large number of samples of full scale sine wave and estimating cumulative histogram. Gain error and offset error are determined from first and last code transition levels of ADC transfer characteristics. ENOB is determined from actual rms error and ideal rms error. Simulation of 5–8 bit ADC transfer characteristics is done and ADC parameters are estimated by introducing arbitrary nonlinearity errors. Comparison of simulation results of this method with existing methods is done and improvement in results is obtained as compared to existing. The main aim of dynamic testing is to determine functional parameters of an ADC which are responsible for the accuracy, resolution, speed and linearity of the conversion process.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

Estimating the effects of ADC parameters on the statistical characteristics of the signal from a simulated optoelectronic system

An effective model is proposed for evaluating the effects of analog-to-digital converter (ADC) errors on the value distribution in the output sequence for any distribution of the input, together with a method of estimating ADC performance for statistical studies on signals.

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST

The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.

Dynamic characterisation of A/D converters using fast Walsh transform

This work presents an application of the Walsh transform to the dynamic characterisation of analog-to-digital converters (ADCs). The Walsh Transform (WT) is an analytical operator that extracts information on ADC parameters at the bit level rather than at the channel level. The use of the WT allows the performance of an ADC to be summarised with a reduced set of values as compared to the conventional set of non-linearity errors. To limit CPU time, a fast algorithm is used to compute the WT. A characterisation environment based on this approach was developed and used to evaluate ADC performance.