Analog-to-digital Converter Design Research Articles

Using Novel One-Bit ADC to Design n-Bit ADC

This work presents two novel styles for designing n-bit analog to digital converter (ADC). Each of the proposed ADCs is built using novel one-bit cell. The novel cell produces single output bit as a response to an input voltage, in addition, it outputs another analog voltage. The generated analog voltage is used again as an input to the to generate one more bit, and new analog voltage, and so on. The proposed n-bit ADC is built using the novel one-bit cell in two different styles. One design style, by connecting n ADC cells together to construct n-bit ADC that produces parallel binary outputs. The other design style realizes the n-bit ADC using single ADC cell and outputs n-bit serially. In both ADC designs introduced in this work, modularity was the main design parameter. The two different n-bit ADCs have been simulated. The first n-bit ADC with parallel outputs produces clean outputs at 50MS/s, and the other ADC design shows clean serial bits at 5KS/s.

A 4-b 7-$\mu$ W Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation

This paper presents a 4-b phase-domain analog-to-digital converter (ADC) that utilizes the time-domain reference generation scheme for low-power operation. Rather than prior arts that rely on power-hungry resistive/current combiners or the IQ-assisted binary-search algorithm with large power T&H circuits for the reference generation, this design benefits from the fully dynamic power characteristic of the time-domain operation, thus leading to an energy-efficient phase ADC design. By introducing several on-chip calibration techniques, the design achieves good robustness with the proposed time-domain operation. The prototype is fabricated in the standard 65-nm CMOS technology, achieving an ENOB of 3.42 bits at 1 MS/s with near Nyquist input, while dissipating 7 μW from a 1-V supply. It leads to a 1.36-pJ/conversion-step Walden Figure of Merit at Nyquist input (FoM@Nyquist).

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

Deep-learning-powered photonic analog-to-digital conversion

Analog-to-digital converters (ADCs) must be high speed, broadband, and accurate for the development of modern information systems, such as radar, imaging, and communications systems; photonic technologies are regarded as promising technologies for realizing these advanced requirements. Here, we present a deep-learning-powered photonic ADC architecture that simultaneously exploits the advantages of electronics and photonics and overcomes the bottlenecks of the two technologies, thereby overcoming the ADC tradeoff among speed, bandwidth, and accuracy. Via supervised training, the adopted deep neural networks learn the patterns of photonic system defects and recover the distorted data, thereby maintaining the high quality of the electronic quantized data succinctly and adaptively. The numerical and experimental results demonstrate that the proposed architecture outperforms state-of-the-art ADCs with developable high throughput; hence, deep learning performs well in photonic ADC systems. We anticipate that the proposed architecture will inspire future high-performance photonic ADC design and provide opportunities for substantial performance enhancement for the next-generation information systems.

Methodologies for CAM and ADC design

Amount of information exchange in modern technology era is increasing rapidly for accommodating both correlated and non-correlated contents. This can be best handled by filling the data as associations (linked data in a pre-defined order), rather than just indexing. Through association, available data are divided into related subsets and stored in a linked fashion. Content addressable memory (CAM) can reduce the time of locating the data that eliminates the following two inevitable issues: 1) The path of address location limits the memory access time and address-line size accounts for the depth (number of entries) in memory; 2) The search content under process is unknown, therefore even for an unavailable data, the full memory is searched. An analog to digital converter (ADC) acts as a primary interfacing device to communicate between the digital processor with real world applications. This work is a continuous study and improvement in various factors involved in the development of CAM and ADC.

Economic Modelling and Implementation of Test Signal Generator for Characterization of Continuous Time Sigma-Delta Analog-to-Digital Converter

Now there is a tremendous growth in the specific applications positively related to wireless communications, which posses the specific requirement for mixed-signal integrated circuits. When these independent circuits are used in the unique design of ADC and DAC practical applications, the considerable complexity of the testing increases. BIST is a precisely conventional technique which typically reduces this considerable complexity and prevents functional dependence on high-cost test equipment ATE. Moreover, in Built-In-self-Test (BIST), the output response analyzer (ORA) is the most significant component of architecture of continuous time (CT) sigma-delta analog-to-digital converter (ADC). There are numerous techniques of ORA used for accurate determining the design parameters like integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise ratio (SNR). In this paper, the prime focus is primarily on the modern CORDIC technique which is used as ORA. For the modelling and accurate simulation of this technique Matlab simulink and CADENCE VIRTUOSO EDA tool environment software are properly implemented. A Coordinate Rotation Digital Computer (CORDIC) reduces the design complexity of the independent circuit. The design of ADC can be improved tremendously by typically using BIST. This paper focuses on the system level modelling of test stimuli generator (TSG) and its simulation for accurate characterization of high-resolution sigma-delta ADC. The successful implementation is carefully tested on Matlab simulink tool environment. The auto-testing external test equipment is required to test the integrated structures. TSG is implemented and it helps in extracting of statics and transmission parameters required for characterization of CT sigma-delta ADC.

A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

Compared to pipelined analog-to-digital converters (ADCs), pipelined- successive approximation register (SAR) ADCs have been actively explored for better energy efficiency in recent years. Nonetheless, the pipelined-SAR architecture inherently limits the sampling speed of the ADC due to the slow operation of the first SAR ADC, which becomes an increasingly important limitation with the recent expansion of high-speed applications. In this paper, we introduce our new design of a pipelined-SAR ADC to enable faster speed. New loop-unrolled architecture with the split capacitor is used for the first SAR ADC to improve the speed. A resistive open-loop multiplying digital-to-analog converter with a new calibration scheme is designed to reduce the power consumption at high speed. As a result, the 65-nm design can achieve 300-MS/s sampling rate with a single channel. It is among the fastest pipelined-SAR ADC design so far. The peak signal-to-noise-and-distortion ratio is 63.6 dB with a 10-MHz input. It consumes 12.5-mW power from a 1.2-V supply to achieve a power efficiency of 34 fJ/conversion-step.

Analog to Digital Converter Performance Testing Based on MATLAB

In this paper, a new calculation method is proposed to seek the performance of the analog-to-digital converter (ADC). During the designing process of the ADC, the parameters would be simulated repeatedly for improving performance, but some parameters cannot be obtained directly through simulating. Therefore, MATLAB is utilized to analyze the simulation output data of the ADC in order to obtain the characteristics values. The MATLAB based calculation algorithm can be applied to performance testing during ADC design and practical measurement of the ADC chip.

Low-Cost, High-Precision DAC Design Based on Ordered Element Matching

Digital-to-analog converter (DAC) is one of the circuits with increasing demands on high-accuracy requirements. However, the cost of existing high-precision DACs is high and difficult to reduce because implementation hardly benefits from the scaling of digital circuits. In this paper, a low-cost, high-precision DAC structure based on ordered element matching (OEM) theory was proposed and its design methodology is discussed. It achieves high matching accuracy by applying the OEM calibration to the resistors in unary weighted segments and calibrating the gain error between different segments by small calibration DAC. A MATLAB behavioral model of a 20-bit R-2R DAC is built, and the statistical results show that the proposed DAC structure can achieve the same accuracy in less than 1/62 resistor area compared with state of the art.

Understanding Metastability in SAR ADCs: Part I: Synchronous

By strongly leveraging technology scaling in its building blocks, the successive approximation architecture resides comfortably at both the high-speed and high-resolution frontiers of the analogto-digital conversion landscape [1]-[3]. This particularly digital-friendly set of building blocks includes MOS switches, metal fringe capacitors, and regenerative latches, each of which has analog nonidealities that can limit the attainable speed and resolution of a successive approximation register (SAR) analog-to-digital converter (ADC). Whereas circuit techniques such as bottom-plate sampling and mismatch calibration have a proven track record for mitigating sources of nonlinearity, techniques that address the problem of metastability in the regenerative latch are still under development [4]-[6]. This two-part tutorial aims to help readers follow the most recent advancements in this area, by providing an all-in-one introduction to the subject of metastability in SAR ADCs not yet available in the literature or textbooks. A clear picture of how metastability, noise, and the SAR algorithm interact is a useful prerequisite for deciding where and how potential metastability errors should be dealt with in the design of SAR ADCs.

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

The need for low-power wireless sensor networks (WSNs) continues to grow. Based on the fact that digital-to-analog converters (DACs) are essential elements in the WSN and consumes a lot of power, this paper presents a new low-power DAC design to realize the low-power WSN. To do that, this paper exploits the dynamic element matching (DEM) technique, one of the well-known techniques for high performance DACs, proposes a lightweight DEM (LW-DEM) technique that minimizes power and area overhead of the DEM technique. More specifically, this paper is motivated from the observation that input data of DACs tends to be sufficiently random that the input data can be used for the random selection of the current source instead of a pseudo-random number generator (PRNG) for the traditional DEM. Because the PRNG consumes a lot of power and occupies a large area in a DAC, elimination of the PRNG from a DAC and utilizing input data result in significant power saving and area reduction in the DAC while meeting the required performance of the low-power WSNs. This paper provides a detailed LW-DEM architecture and its operation principle. To demonstrate the efficacy of the proposed method, a prototype 12-bit DAC using the LW-DEM is implemented. The 12-bit DAC is fabricated in 65 nm CMOS technology and occupies only $0.065~{mm}^{2}$ area. Measurement results with the prototype verify that the DAC using LW-DEM accomplishes 39% power saving and 52% area reduction in the randomizer, compared to a DAC using the conventional DEM. At the same time, the measured spurious-free dynamic range (SFDR) of the DAC using LW-DEM is better than 55 dB, demonstrating that the proposed DAC achieves almost same performance as a DAC using the conventional DEM.

Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic

High-performance, low-power-consumption, and high-accuracy analog-to-digital converters (ADCs) with a compact area are necessary for a wide range of current applications. This paper presents a pipeline ADC architecture with a novel 3-D clock distribution network utilizing through-silicon via-induced benefits. It also implements memristor ratioed logic as the basic elements of digital error correction subblock to further decrease the area, delay, and power consumption. In addition, an optimization technique using computational intelligence is applied to maximize the overall system performance. The proposed 3-D pipeline ADC is designed in a 65-nm CMOS technology and shows significant improvement regarding dynamic performance, energy efficiency, area, and clock accuracy compared with that of conventional 2-D ADC designs.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

Portable low power and high quality monitoring devices play an important role for improving the performance of wireless body sensor networks. Mixed signal processor is required in ECG monitoring unit that comprises of analog front end, analog to digital converter (ADC) and digital signal processor. ADC is a core element in mixed signal processing unit and the proper design of ADC is crucial for data acquisition without losing heart related information and originality. The adaptive sampling has been used in the existing ADCs for choosing the sampling clock adaptively. Adaptive sampling rate ADC performs compression and reduces power consumption to some extent, however low powers ADCs are essential in wireless healthcare monitoring systems. In this paper, fuzzy logic based variable resolution controller is proposed to design the ADC efficiently in terms of circuit complexity and power. To further reduce the power consumption, power gating technique is adopted for static power reduction. Under 90 nm CMOS technology, gate count, core area utilization and power consumption have been determined for existing adaptive sampling ADC and fuzzy logic based adaptive sampling ADC. Cadence design tools have been used for the measurement of power in the designed circuit. The performance has been found to be better in terms of area and power that are very much essential for wireless ECG monitoring systems.

SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices

This paper devises a novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities. The beyond-CMOS hardware architecture has been designed to minimize the overall cost of signal acquisition. Spin-Hall Effect driven Domain Wall Motion (SHE-DWM) devices are utilized to realize the proposed framework called Spin-based Logic-In-Memory ADC (SLIM-ADC). Our simulation results indicate that the proposed SLIM-ADC offers ∼200 fJ energy consumption on average for each analog conversion or logic operation with up to 1 GHz speed. Furthermore, our results indicate that the proposed SLIM-ADC outperforms other state of the art spin-based ADC designs by offering ∼5.45 mW improved power dissipation on average. Additionally, a Majority Gate (MG)-based Full-Adder (MG-FA) is implemented using the proposed SLIM-ADC. Our results show that the proposed MG-FA offers ∼2.9-fold reduced power dissipation on average and ∼1.7-fold reduced delay on average compared to the state of the art Full-Adder designs reported herein.

Design and implementation of reliable flash ADC for microwave applications

Analog to Digital Converter (ADC) is a necessary component of mixed signal designs. It converts the analog signal to the digital signal so that it is used as a bridge. This paper proposes R-Flash ADC (Reliable Flash ADC) which combines an area efficient multiplexer pass gate (MPG) encoding technique and low power ITIQ (Improved Threshold Inverter Quantization) comparator. The proposed Flash ADC is implemented using tanner EDA with 125 nm technology. R-Flash ADC reduces the number of transistors by 39% and reduces the power consumption by 59% with high resolution quality when compared to Mux TIQ ADC. The reliability analysis shows that the proposed R-Flash ADC has reliability of 95% and it overcomes the existing techniques as well.

Outage Probability Analysis and Resolution Profile Design for Massive MIMO Uplink With Mixed-ADC

This paper analyzes the outage probability for the uplink of multi-user massive multi-input-multi-output systems with a mixed analog-to-digital converter (ADC) architecture, in which the base station (BS) is equipped with ADCs of different resolution levels. Maximum-ratio combining (MRC) is used at the BS. By deriving the distribution of the user-interference power and statistical properties of other components in the signal-to-interference-plus-noise-ratio (SINR), a tight closed-form approximation for the outage probability is obtained for a general mixed ADC structure with any resolution profile. Then, two methods for the ADC resolution profile optimization are proposed considering both the outage probability and the BS energy consumption. The first method uses low-complexity incremental search to minimize the BS energy consumption for given outage probability constraint. The other method is based on multi-objective optimization and adopts a discrete-variation of the classic non-dominated sorting genetic algorithm II (NSGA-II). Numerical results are presented to validate the outage probability results. Furthermore, it is shown that the two proposed mixed-resolution ADC designs largely outperform a two-level ADC structure and provide more choices than the uniform ADC structure for resolving the tradeoff between outage probability and BS energy consumption.

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET

In this brief, a novel programmable low power analog-to-digital converter (ADC) circuit design is proposed using independently driven underlap double gate MOSFET (IDUDGMOS) to operate in radio frequency domain and its performance is studied. The primary motivation of the design is to eliminate the need for a resistor ladder for reference voltage selection and to minimize the number of transistor used in the flash ADCs. The proposed design utilizes the back gate voltage controllability of IDUDGMOS for varying reference voltage of the comparators in the ADCs. The parameters of the designed ADC analyzed are the bandwidth, the linearity, and the power consumption of the circuit. The proposed circuit offers wider bandwidth and lower power consumption compared to earlier ADC designs.

Architecture optimization for energy-efficient resolution-scalable 8–12-bit SAR ADCs

Low power analog-to-digital converters (ADCs) in energy constrained devices, such as wireless sensor readout modules, often target dynamic resolution scalability with application context to reduce the average power consumption. This work implements such an 8–12-bit resolution scalable ADC, using an oversampling and noise-shaping successive approximating register (SAR) architecture. This architecture is selected for its high power efficiency after a detailed comparison of various resolution enhancing techniques within the SAR framework. Specifically, in this paper, three resolution enhancing techniques are reviewed and compared on their energy usage namely: the majority voting, the oversampling, and the oversampling with noise shaping SAR ADC. Furthermore, the proposed resolution scalable ADC simplifies the design of the noise shaping filter by enabling the use of a first order switched-capacitor low-pass filter for shaping the comparator noise and the in-band quantization noise. The ADC design also alleviates the matching concerns by using only an 8-bit capacitive digital-to-analog converter (DAC) for a maximum 12-bit resolution, or 11-bit effective number of bits (ENOB). The architecture can be configured to allow an operation from 8-bit traditional SAR ADC up to an 11-bit ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with up to 320 kS/s and achieves a power scaling from 80 nW to 1.5 $$\upmu$$ W, resulting in an steeper energy-ENOB scaling trend compared to state-of-the art resolution scalable ADCs.

A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication

The growing need for power aware and energy efficient analog-to-digital converters (ADCs) has led to the development of optimized ADC designs. Though several ADCs are designed using isolated platforms, the usage of hybrid combination has noticeably made an impact in achieving this scenario. The proposed work herein is based on a subranging flash and successive-approximation-register ADC design. The isolated architectures have been redesigned and it is seen to be efficient with a power reduction by 40%. The utilization of comparator with a proposed charge sharing circuitry produces a lower input referred offset voltage during the comparison stages by eliminating the need of a extra circuitry. However, this increases the kick-back noise accounting for the sure trade-off. To reduce these effects a sample and hold switch is used at the comparator input voltage during the decision mode to minimize the kick-back noise thereby keeping the non-linearity errors at minimal. Energy efficiency of 64% have been seen compared to the referred design due to the proposed charge sharing circuitry during the evaluation phase. The converter achieves 61-dB SFDR and 46.5-dB SNDR at 2.5 GS/s for input signal frequency of 100 MHz with a power dissipation of 10.5 mW at 1 V supply.

Analysis and Comparison of High-Resolution GS/s Samplers in Advanced BiCMOS and CMOS

High-speed and high-resolution analog to digital converters (ADCs) (10+ bits) are essential components of modern wireless communication systems and mmWave radios. Their performance is often limited by the noise and distortion from the front-end samplers, the design of which can be challenging. Modern ADC design has moved heavily to scaled CMOS technologies due to its attractive digital and integration capabilities, but these processes face challenges of high fabrication costs, and diminishing analog performance that has to be bolstered by extensive digital calibration. On the other hand, BiCMOS processes have advanced and scaled sufficiently that they may be able to offer the best of the mixed signal world. This brief examines, both theoretically and through simulations, the design of samplers for high-speed, low-distortion in CMOS and BiCMOS for GS/s ADCs. Two fully differential samplers, with an equivalent sampling frequency of 5 GS/s and an input frequency range of up to 10 GHz, are designed in a 90-nm BiCMOS and a 28-nm CMOS process, respectively, and their distortion performance is analyzed, simulated, and compared.