Understanding Metastability in SAR ADCs: Part I: Synchronous

Abstract

By strongly leveraging technology scaling in its building blocks, the successive approximation architecture resides comfortably at both the high-speed and high-resolution frontiers of the analogto-digital conversion landscape [1]-[3]. This particularly digital-friendly set of building blocks includes MOS switches, metal fringe capacitors, and regenerative latches, each of which has analog nonidealities that can limit the attainable speed and resolution of a successive approximation register (SAR) analog-to-digital converter (ADC). Whereas circuit techniques such as bottom-plate sampling and mismatch calibration have a proven track record for mitigating sources of nonlinearity, techniques that address the problem of metastability in the regenerative latch are still under development [4]-[6]. This two-part tutorial aims to help readers follow the most recent advancements in this area, by providing an all-in-one introduction to the subject of metastability in SAR ADCs not yet available in the literature or textbooks. A clear picture of how metastability, noise, and the SAR algorithm interact is a useful prerequisite for deciding where and how potential metastability errors should be dealt with in the design of SAR ADCs.