Analog-to-digital Converter System Research Articles

High precision measurement method for dynamic transient signal based on compressed sensing and spline polynomial interpolation.

During the measurement of dynamic transient signals, a high sampling frequency brings great challenges to the analog-to-digital converter (ADC) and testing system. To address these issues, a high precision measurement method for dynamic transient signals is first proposed in this paper. The characteristics of dynamic transient signals are analyzed first. On the basis of this, a random sampling method combining compressed sensing (CS) with spline polynomial interpolation (SPI) is put forward. The fusion of the two algorithms can effectively reduce the quantity of sampling and observation points to reduce the requirement of the ADC and testing system for transient signal measurement and to improve the observation efficiency of the existing uniform sampling. Finally, a Machete hammer test platform for dynamic transient signals is established. A series of simulation and experimental results validate that the error of data reconstruction using the random sampling method combining CS with SPI is not greater than 5.1%.

Quantized Massive MIMO Systems With Multicell Coordinated Beamforming and Power Control

In this paper, we investigate a coordinated multipoint (CoMP) beamforming and power control problem for base stations (BSs) with a massive number of antenna arrays under coarse quantization at low-resolution analog-to-digital converters (ADCs) and digital-to-analog converter (DACs). Unlike high-resolution ADC and DAC systems, non-negligible quantization noise that needs to be considered in CoMP design makes the problem more challenging. We first formulate total power minimization problems of both uplink (UL) and downlink (DL) systems subject to signal-to-interference-and-noise ratio (SINR) constraints. We then derive strong duality for the UL and DL problems under coarse quantization systems. Leveraging the duality, we propose a framework that is directed toward a twofold aim: to discover the optimal transmit powers in UL by developing iterative algorithm in a distributed manner and to obtain the optimal precoder in DL as a scaled instance of UL combiner. Under homogeneous transmit power and SINR constraints per cell, we further derive a deterministic solution for the UL CoMP problem by analyzing the lower bound of the SINR. Lastly, we extend the derived result to wideband orthogonal frequency-division multiplexing systems to optimize transmit power and beamformer for all subcarriers. Simulation results validate the theoretical results and proposed algorithms.

A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

Advanced Receiver Architectures for Millimeter-Wave Communications with Low-Resolution ADCs

Employing low-resolution analog-to-digital converters (ADCs) for millimeter-wave receivers with large antenna arrays provides an opportunity to efficiently reduce power consumption of the receiver. Reducing ADC resolution, however, results in performance degradation due to non-negligible quantization error. In addition, the large number of radio frequency chains is still not desirable. Accordingly, conventional low-resolution ADC systems require more efficient designs to minimize the cost and complexity while maximizing performance. In this article, we discuss advanced low-resolution ADC receiver architectures that further improve the spectral and energy efficiency trade-off. To reduce both the numbers of RF chains and ADC bits, hybrid analog and digital beamforming is jointly considered with low-resolution ADCs. We explore the challenges in designing such receivers and present key insights on how the advanced architectures overcome such challenges. As alternative low-resolution ADC receivers, we also introduce receivers with learning-based detection. The receiver does not require explicit channel estimation, and thus is suitable for one-bit ADC systems. Finally, future challenges and research issues are discussed.

An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture

Oversampling sigma–delta (Σ–Δ) analog-to-digital converters (ADCs) are currently one of the most widely used architectures for high-resolution ADCs. The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed. Structurally, the Σ–Δ ADC is divided into two parts: a front-end analog modulator and a back-end digital filter. The performance of the front-end analog modulator has a marked influence on the entire Σ–Δ ADC system. In this paper, a 4-order single-loop switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) structure is proposed. Based on the chosen modulator architecture, the ASIC circuit is implemented using a chartered 0.35 μm CMOS process with a chip area of 1.72 × 0.75 mm2. The chip operates with a 3.3-V power supply and a power dissipation of 22 mW. According to the results, the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits (ENOB) was almost 18-bit.

Fully Integrated Organic Field‐Effect Transistor Platform to Detect and to Quantify NO2 Gas

Herein, the gas sensing characteristics of PDVT‐10 organic field‐effect transistor (OFET) devices are explored and integrated to build a compact analog‐to‐digital converter (ADC) gas detection system. The electrical characteristics of the pristine PDVT‐10 OFET exhibit Ion/Ioff ratio and threshold voltage as 104 and −12 V, respectively. Through the coating of a metal‐organic framework (MOF) on the surface of PDVT‐10, the Ion/Ioff improves by one order of magnitude accompanied by significant positive threshold shift measured around 4 V. MOF is added as a pre‐concentrating material, and the device exhibits excellent selectivity and good sensitivity toward the target NO2 gas. Most of the reports available in the literature generally focus on the gas sensing performance of individual sensors, which does not have the potential to solve real‐time sensing problems. Hence, for the first time, a fully integrated ADC system is designed with just two OFETs. The integrated ADC system not only detects the NO2 gas with high sensitivity and selectivity but also generates a 5 bit digital output corresponding to different NO2 gas concentrations from 25 ppb to 1 ppm.

Base Station Antenna Selection for Low-Resolution ADC Systems

For low-resolution analog-to-digital converter (ADC) systems, only high-complexity receive antenna selection has been developed and transmit antenna selection has been limited to a single antenna selection in prior work. In this paper, we propose low-complexity receive antenna selection algorithms and analyze transmit antenna selection by considering antenna selection at a base station with large antenna arrays and low-resolution ADCs. For downlink antenna selection, we show a selection criterion with zero-forcing precoding equivalent to a perfect quantization system; sum rate increases with number of selected antennas; derivation of the sum rate loss function from using a antenna subset; and sum rate loss reaches a maximum at a point of total transmit power and decreases beyond that point to converge to zero. For wideband orthogonal-frequency-division-multiplexing (OFDM) systems, our results hold when entire subcarriers share a common subset of antennas. For uplink antenna selection, we generalize a greedy antenna selection criterion; propose a quantization-aware fast antenna selection algorithm using the criterion; and derive a lower bound on sum rate achieved by the proposed algorithm. For wideband OFDM systems, we extend our algorithm and derive a lower bound on its sum rate. Simulation results validate theoretical analyses and show increases in sum rate over conventional algorithms.

Deep-learning-powered photonic analog-to-digital conversion

Analog-to-digital converters (ADCs) must be high speed, broadband, and accurate for the development of modern information systems, such as radar, imaging, and communications systems; photonic technologies are regarded as promising technologies for realizing these advanced requirements. Here, we present a deep-learning-powered photonic ADC architecture that simultaneously exploits the advantages of electronics and photonics and overcomes the bottlenecks of the two technologies, thereby overcoming the ADC tradeoff among speed, bandwidth, and accuracy. Via supervised training, the adopted deep neural networks learn the patterns of photonic system defects and recover the distorted data, thereby maintaining the high quality of the electronic quantized data succinctly and adaptively. The numerical and experimental results demonstrate that the proposed architecture outperforms state-of-the-art ADCs with developable high throughput; hence, deep learning performs well in photonic ADC systems. We anticipate that the proposed architecture will inspire future high-performance photonic ADC design and provide opportunities for substantial performance enhancement for the next-generation information systems.

Analysis of Ergodic Rate for Transmit Antenna Selection in Low-Resolution ADC Systems

In this paper, we analyze the ergodic rate of single transmit antenna selection (TAS) in low-resolution analog-to-digital converter (ADC) systems. Using low-resolution ADCs is a potential power-reduction solution for multiple antenna systems. Low-resolution ADC systems with TAS can further reduce cost and power consumption in wireless transceivers. Considering such systems, we derive the approximated lower bound of the ergodic rate with TAS. Here, we exploit the approximated distribution of the sum of Weibull random variables to address the challenge involved in analyzing the quantization error. We, then, derive the approximated ergodic rate with TAS for a single receive antenna in closed form, which reveals the TAS gain in low-resolution ADC systems. The upper bound of a single transmit and single receive antenna system under coarse quantization is derived to compare with the ergodic rate of the TAS system. The analysis shows that the TAS method achieves a large improvement in ergodic rate with a moderate number of transmit antennas. Simulation results validate the derived ergodic rates and resulting intuition.

Real-time self-adaptive calibration method for high speed acquisition system.

The main factors that enable capture of complex and transient signals in real-time are improved sampling rates and processing speeds. The time-interleaved architecture is an effective method that allows systems to break through the speed bottleneck of single analog-to-digital converters (ADCs) and go beyond the state-of-the-art process technology limit. However, the performance of the acquisition system may be reduced because of the offset, gain, and time mismatch errors that occur in time-interleaved ADC systems. To correct these errors, this paper first proposes a self-adaptive correction algorithm and then introduces real-time solutions for this algorithm. Finally, the proposed calibration method is implemented in a digital phosphor oscilloscope. Simulations and experimental testing indicate that this system shows good real-time performance and provides a high dynamic performance with an effective number of bits of 7.3 bits and a signal-to-noise ratio of 45.5574 dB.

Performance Analysis of Protograph LDPC Codes Over Large-Scale MIMO Channels With Low-Resolution ADCs

Protograph LDPC (P-LDPC) codes and large-scale multiple-input multiple-output (LS-MIMO) are cornerstones of 5G and future wireless systems, thanks to their powerful error-correcting capability and high spectral efficiency. To alleviate the high complexity in signal detection/decoding that dramatically grows with the number of antennas (in the order of tens or even hundreds), low-resolution analog-to-digital converters (ADCs) and joint detection and decoding using factor graph have recently attracted paramount interest. Unlike high-resolution ADCs, by using a small number of bits to quantize the received signal, low-resolution ADCs help reduce the hardware cost and power consumption of the RF circuit of practical LS-MIMO transceivers. Such a very much desirable reduction comes at the cost of additional quantization noise, introduced by low-resolution ADCs. This work aims to provide a unified framework to analyze the impact of the low-resolution ADCs on the performance of P-LDPC codes in practical LS-MIMO systems. It is worth noting that the previous analytical tools that have been used to evaluate the performance of P-LDPC codes do not account for the quantization noise effect of the low-resolution ADCs and the fact that the covariance of quantization noise depends on the fading channels. This article addresses this shortcoming by first leveraging the additive quantization noise model. We then derive the expression of extrinsic information for the belief-propagation LS-MIMO detector. The mutual information functions, which are the core elements of our proposed protograph extrinsic information transfer (PEXIT) algorithm, are analyzed for LS-MIMO communication systems. Our proposed PEXIT algorithm allows us to analyze and predict the impact of the low-resolution ADCs on the performance of P-LDPC codes, considering various input parameters, including the LS-MIMO configuration, the code rate, and the maximum number of decoding iterations, and the code structure. Based on our extensive analytical and simulation results, we found that the performance of 3-bit and 4-bit ADC systems only have a small gap to that of the unquantized systems. Especially when the 5-bit ADC scheme is applied, the performance loss is negligible. This finding sheds light on the practical design of LS-MIMO systems using P-LDPC codes.

New data acquisition system for beam loss monitor used in J-PARC main ring

A new data acquisition system has been developed continually as a part of the development of a new beam loss monitor (BLM) system for the J-PARC main ring. This development includes a newly designed front-end isolation amp that uses photo-couplers and a VME-based new analog-to-digital converter (ADC) system. Compared to the old amp, the new amp has a 10 times higher conversion impedance for the input current to the output voltage; this value is 1 MΩ. Moreover, the bandwidth was improved to from DC to 50 kHz, which is about two orders of magnitude greater than the previously used bandwidth. The theoretical estimations made in this study roughly agree with the frequency response obtained for the new system. The new ADC system uses an on-board field-programmable gate array chip for signal processing. By replacing the firmware of this chip, changes pertaining to future accelerator upgrade plans may be introduced into the new ADC system; in addition, the ADC system can be used in other applications. The sampling speed of the system is 1 MS/s, and it exhibits a 95 dBc spurious-free dynamic range and 16.5 effective number of bits. The obtained waveform and integrated charge data are compared with two reference levels in the ADC system. If the data exceeds the reference level, the system generates an alarm to dump the beams. By using the new data acquisition system, it was proved that the new BLM system shows a wide dynamic range of 160 dB. In this study, the details of the new data acquisition system are described.

Exploiting Smallest Error to Calibrate Non-Linearity in SAR Adcs

This paper presents a statistics-optimized organization technique to achieve better element matching in successive approximation register (SAR) analog-to-digital converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on a spurious free dynamic range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch $\sigma _{u}=0.2\%$ in a 14-bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimization and strategy optimization, the performance boosting on the SFDR can be effectively achieved. Such a great improvement on the resolution of the ADC only requires an off-line pre-processing digital part.

Optical sampling analog-to-digital converter based on two asynchronous mode-locked fiber lasers

Using a mode-locked fiber laser in an electronic analog-to-digital converter (ADC) system has attracted increasing attention because an optical pulse train, generated by an optical mode-locked fiber laser, has an ultrashort pulse width and ultralow timing jitter compared with an electronic pulse train. An optical sampling ADC system based on a mode-locked fiber laser has made great progress in high-speed microwave signal ADC systems with high resolution. In this paper, we report an optical sampling ADC system based on two mode-locked fiber lasers with a slight difference in repetition frequency. Working with the Chinese remainder theorem, we can determine the microwave whose frequency is far greater than the sampling rate. We can precisely measure carrier frequency with a subsampling method. The optical ADC system can digitize a narrow bandwidth at high carrier frequency. In our system, the repetition rate of one mode-locked fiber laser is 100 MHz, and the other is (100 M+1 k) Hz. We digitize a narrow bandwidth (<50 MHz) microwave signal on a 10 GHz carrier frequency with greater than 7 effective-number-of-bit (ENOB) resolution.

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

Optimal Design of Secrecy Massive MIMO Amplify-and-Forward Relaying Systems With Double-Resolution ADCs Antenna Array

This paper focuses on a secrecy constrained massive multiple-input multiple-output (MIMO) relaying system in terms of the optimal design of system parameters such as the optimal total number of antennas at relay, where a more practical mixed analog-to-digital converters (ADCs) scheme, double-resolution ADCs scheme, is proposed. In the proposed double-resolution ADCs scheme, the total $M$ antennas at relay are divided into two parts, one of which includes $M_{0}$ antennas with medium-resolution ADCs only requiring 5~12 quantization bits and the remainder of which consists of $M_{1}$ antennas with low-resolution ADCs. The transmission from relay to destinations is exposed to a passive eavesdropper. For such massive MIMO relaying systems, we first derive the total achievable ergodic rates of legitimate users as well as the corresponding secrecy outage rates. Then, a reasonable energy consumption model is modeled so that the secrecy energy efficiency (SEE) is derived, where the effect of the source power, the resolutions of ADCs, and the ratio of the antenna numbers with medium- and low-resolution ADCs are exploited perfectly. The presented numerical results show that replacing high-resolution ADCs with medium-resolution ADCs is beneficial for improving the system SEE while the effect on the total achievable rate is very small. Specially, three main insights are achieved: 1) there exists an optimal value of the source power at which the SEE is optimal; 2) with given ratio $M_{0} :M_{1} $ , the optimal value of quantization bits of medium-resolution ADCs is upper-bounded, under which the system has higher SEE, that is to say, we obtain the upper bound of the resolution of the medium-resolution ADCs; and 3) the optimal number of the total antennas is impacted jointly by the number $b_{0}$ of the quantization bits of medium-resolution ADCs and the ratio $M_{0} :M_{1}$ . Specially, while the optimal number of the total antennas is 100 or so for the pure high-resolution ADCs systems, the one for the proposed double-resolution ADCs systems would up to 500~700. Moreover, the optimal antenna number is increasing with the decrease of $b_{0} $ and the ratio $M_{0} :M_{1} $ so that the system performance can be improved further.

A CONTINUOUS-TIME ADC AND DIGITAL SIGNAL PROCESSING SYSTEM FOR SMART DUST AND WIRELESS SENSOR APPLICATIONS

In this paper an event-driven (ED) digital signal processing system (DSP), Analog-to-digital converter (ADC) and Digital-to-analog converter (DAC) operating in continuous-time (CT) with smart dust as the target application is presented. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clock less EDADC system based on a CT delta modulation (DM) technique is used. The ADC output is digital data, continuous in time, known as “data token”. The ADC used an un buffered, area efficient, segmented resistor string (R-string) feedback DAC. This DAC in component reduction with prior art shown nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained Signal to noise distortion ratio (SNDR) for the 8-bit ADC system is 55.73 dB, with the band of interest as 220 kHz and Effective number of bits (ENOB) of more than 9 bits. Index Terms: smart dust, continuous-time (CT), Delta modulation, Analog-to-digital converter (ADC), Digital-to –analog converter (DAC)

Photonic analog-to-digital converter based on the robust symmetrical number system

A novel approach to realizing photonic analog-to-digital conversion with Gray-code-like property is proposed and demonstrated. Instead of using Mach–Zehnder modulators (MZMs) with different half-wave voltages, an array of MZMs with identical half-wave voltages are applied to realize quantization and encoding, which greatly simplifies the implementation. Multiple comparators with preset thresholds are applied at the output of each MZM to improve the number of bits. Through properly setting the bias voltages of the MZMs, a photonic analog to digital converter (ADC) based on the robust symmetrical number system (RSNS) coding method is realized. As an example, a 3-channel structure with maximum quantization level of 17 (corresponding to 4.09 bits) is investigated in detail. We show that the differential encoding technique can be applied in the proposed structure, which increases the equivalent number of bits of the ADC system.

Bit-Resolution Improvement of an Optically Sampled Time-Interleaved Analog-to-Digital Converter Based on Data Averaging

In this paper, we present an experimental method demonstrating an improvement in the resolution of optically sampled time-interleaved analog-to-digital converters (ADCs) by applying a data averaging technique. We implemented two experiments for oversampling four times the bandwidth of an analog input signal using a multichannel time-interleaved arrangement. The sampling rate for each experiment was 2.08 gigasamples per second. In the first experiment, the optically sampled signal of each channel is digitized by a single ADC, whereas in the second, the signal is simultaneously digitized by four ADCs, and thereafter, the four digitized samples are averaged. A 20-dBm white-noise signal was superimposed on the input analog signal to test the implemented ADC systems. An improvement in the signal-to-noise-and-distortion ratio from 55.58 to 61.44 dB was achieved with averaging. Likewise, an improvement in the effective number of bits from 8.94 to 9.91 was achieved with averaging.

Volterra Series Modeling for Analog to Digital Converters

The modeling for Analog to Digital Converters (ADCs) has been largely applied in recent years for digital postcalibration. In this paper, according to the existing modeling methods, the Volterra series can be used to mathematically model the ADCs system. Preliminary experimental results, which validate the proposed approach, are presented in the paper to show the correctness of the Volterra series modeling.