Analog-to-digital Converter Channels Research Articles

Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.

Digital instantaneous frequency measurement with wide bandwidth for real-valued waveforms using multiple sub-Nyquist channels

In order to break through the bandwidth limitation of digital instantaneous frequency measurement for a real-valued waveform, we developed a frequency estimator with a high dynamic range and low computation cost using multiple sub-Nyquist analog to digital converter (ADC) channels. The procedures of the proposed scheme are as follows: (a) perform zero-crossing detection on the real-valued signal and use multiple sub-Nyquist ADC channels to sample the output signal; (b) take several samples of each channel to calculate the folded frequency; (c) use the frequency residuals of each channel to reconstruct the frequency based on the Chinese remainder theorem. Finally, the algorithm robust analysis and simulation experiments are performed, demonstrating that the scheme of this paper has relatively good anti-noise ability and dynamic adaptability.

ICARUS-Q: Integrated control and readout unit for scalable quantum processors.

We present a control and measurement setup for superconducting qubits based on the Xilinx 16-channel radio-frequency system-on-chip (RFSoC) device. The proposed setup consists of four parts: multiple RFSoC boards, a setup to synchronize every digital to analog converter (DAC) and analog to digital converter (ADC) channel across multiple boards, a low-noise direct current supply for tuning the qubit frequency, and cloud access for remotely performing experiments. We also designed the setup to be free of physical mixers. The RFSoC boards directly generate microwave pulses using sixteen DAC channels up to the third Nyquist zone, which are directly sampled by its eight ADC channels between the fifth and the ninth zones.

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively.

An 8-Gs/s 12-Bit TIADC System With Real-Time Broadband Mismatch Error Correction

High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent work on design of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch correction algorithms in FPGA devices, over a broad band of input signal frequencies. Tests were also conducted to evaluate the systems performance, and the results indicate that the Effective Number of Bits (ENOB) is enhanced to be better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after correction, almost the same with that of the ADC chip employed.

Multiplexing readout method based on switch arrays for position sensitive thermal neutron detectors

To address complexities arising from the increased number of readout channels in large scale neutron detection or imaging systems, a multiplexing readout method is introduced. The proposed method can greatly reduce the scale and cost of the readout electronics. To evaluate the readout method, a prototype involving a front-end circuit and a signal multiplexed circuit for detectors such as multiwire proportional chamber (MWPC), gaseous electron multipliers (GEM) and micro-channel plates (MCP) is evaluated in the laboratory. The multiplexing circuit consists of a switch array and a high speed analog to digital converter (ADC). By controlling the switch timing, multi-channel signals can be readout through only one ADC channel, thereby reducing the number of channels required for readout. Furthermore, the readout speed can be adjusted by changing the switching frequency. The results show that the multiplexing readout method is feasible, and the position resolution for thermal neutron detectors is good. The evaluation board is used to simulate the MWPC detector with 2 mm spacing and a position resolution of 35 μm is obtained with event rate up to 2 MHz. Besides, joint test with a thick gaseous electron multipliers (TGEM) detector with 0.8 mm spacing yields a position resolution of about 400 μm.

Non-magnetic compliant finger sensor for continuous fine motor movement detection.

A non-magnetic MEG compatible device has been developed that provides continuous force and velocity information. Combined with MEG, this device may find utility in characterizing brain regions associated with force and velocity relative to individual digits or movement pattern. 15 healthy right-handed participants were given visual cues to perform random finger movements on the prototype finger sensor for 21s and then rest for 21s (7 times). Respective finger flexion data were obtained, during 151-channel MEG brain scanning, by feeding the signal from finger sensor into four input Analog to Digital Converter (ADC) channels in the MEG hardware. The source activity was reconstructed in beta band using a Linearly Constrained Minimum Variance (LCMV) beamformer in the beta band. The ADC channels were used as regressors for a continuous time General Linear Model (GLM) and a Region of Interest (ROI) was identified to examine activity. MEG analysis showed bilateral activation in the primary motor cortex region. Because individual digits could be isolated in the ADC data, somatotopy of the fingers were observed consistent with the homunculus except pinky finger. The total span was calculated to be 5.5662mm. The study confirms that the finger sensor is magnetically compatible with MEG measurements and may potentially provide a means to study complex sensorimotor functions. Improved isolation of individual digit information along with the use of machine learning algorithms can help retrieve more accurate results.

Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC for Readout of Particle Physics Detectors

The design and measurement results of an ultra-low power multi-channel fast 10-bit Analog-to-Digital Converter (ADC) ASIC, developed for readout systems in future particle physics experiments, are discussed. An 8-channel prototype with a PLL-based data serialization and a fast data transmission was designed and fabricated in a 130 nm CMOS process. The ADC converts analog data with sampling rates from about 10 kS/s to 40 MS/s, with power consumption proportional to sampling rate. The resulting Figure of Merit (FOM), for sampling rates 5–40 MS/s, is 35–42 fJ/conv.-step, per ADC channel. Similar power contribution is spent for fast data serialization and the largest contribution goes to data transmission. A wide spectrum of static and dynamic measurements confirm very good performance of this multi-channel ADC with ENOB ${\sim } 9.2$ bits, an excellent channel uniformity, and negligible crosstalk. The ADC works asynchronously and so it is not limited to systems with uniform time sampling. The ADC is designed using dynamic circuitry which eliminates static power consumption (except leakage), as a consequence it is ready for applications requiring power cycling.

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an additional time-shifted ADC channel. The sign of the reference slope, which is the estimated sign of the ideal derivative at the sampling edge of the reference ADC, is matched against the sign of the error value to determine if the timing mismatch is leading or lagging the sampling edge of the reference ADC. The proposed algorithm aligns the sampling edge of each subchannel to that of the reference ADC by handling only two sign bits and thus reduces the timing mismatches with only negligible hardware overhead consisting of simple logic gates.

A Column-Parallel Inverter-Based Cyclic ADC for CMOS Image Sensor With Capacitance and Clock Scaling

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18-μm technology with 110 column-parallel ADC channels and 10.08-μm × 750-μm column pitch. The 3.5/-2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2-μs sampling rate with 120-μW power consumption per channel.

Heterodyne detection and transmission of 60-Gbaud PDM-QPSK signal with SE of 4b/s/Hz.

We experimentally demonstrate 8 × 240-Gb/s super-Nyquist wavelength-division-multiplexing (WDM) polarization-division-multiplexing quadrature-phase-shift-keying (PDM-QPSK) signal transmission on a 50-GHz grid with a net spectral efficiency (SE) of 4b/s/Hz adopting hardware-efficient simplified heterodyne detection. 9-ary quadrature-amplitude-modulation-like (9QAM-like) processing based on multi-modulus blind equalization (MMBE) is adopted to reduce analog-to-digital converter (ADC) bandwidth requirement and improve receiver sensitivity. The transmission distance at the soft-decision forward-error-correction (SD-FEC) threshold of 2 × 10(-2) is 2 × 420 km based on digital post filtering while largely extended to over 5 × 420 km based on 9QAM-like processing, which well illustrates 9QAM-like processing is more efficient for heterodyne coherent WDM system. Moreover, only two ADC channels are needed for simplified heterodyne detection of one 60-Gbaud PDM-QPSK WDM channel, and thus only one commercial oscilloscope (OSC) with two input ports can work well for each WDM channel.

Ultra-low-power radiation hard ADC for particle detector readout applications

Radiation hard analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130 nm CMOS process and it achieves 12-bit resolution, 25 MS/s sampling speed, 15 mW power consumption and hardness to at least 1.8 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The readout of the Liquid Argon Calorimeter of the ATLAS detector in the planned High-Luminosity Large Hadron Collider is one possible application for this ADC.

A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

This paper presents a power- and area-efficient 24-way time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) that achieves 2.8 GS/s and 8.1 ENOB in 65 nm CMOS. To minimize the power and the area, the capacitors in the capacitive DAC are sized to meet the thermal noise requirements rather than the matching requirements, leading to the LSB capacitance of 50 aF. An on-chip digital background calibration is used to calibrate the capacitor mismatches in individual ADC channels, as well as the inter-channel offset, gain and timing mismatches. Measurement results at the 2.8 GS/s sampling rate show that the ADC chip prototype consumes 44.6 mW of power from a 1.2 V supply while achieving peak SNDR of 50.9 dB and retaining SNDR higher than 48.2 dB across the entire first Nyquist zone with a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$1.8{\rm V} _{{\rm pp}\mathchar"702D {\rm diff}}$</tex> </formula> input signal. The prototype chip occupies an area of 1.03 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 1.66 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> , including the pads and the testing circuits. The figure of merit (FoM) of this ADC, calculated with the minimum SNDR in the first Nyquist zone, is 76 fJ/conversion-step.

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC.

NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS

An analog-to-digital converter (ADC) circuit is proposed that utilizes the linearity of the single-bit first-order sigma-delta in a first mode technique. In a second mode, successive approximation is used to convert the remaining voltage from the first conversion to increase the resolution without significantly increasing the conversion time. Both operations can be made in the same hardware, and only a counter is needed as decimation filter so that the converter becomes both area and power efficient. A channel of the ADC implemented in standard CMOS occupies an area of 40/spl times/1640 /spl mu/m/sup 2/. The control logic and reference voltage generation circuits, common for the ADC array, occupy a similar area. Estimated power consumption per ADC channel is about 0.5 mW including reference voltage generation. The conversion speed per ADC channel is 12.8 ksamples/s at a clock rate of 3.4 MHz. The ADC concept is suitable whenever a high resolution at a moderate speed is needed.