Analog Signal Processing Research Articles

Generalized Framework for Hybrid Analog/Digital Signal Processing in Massive and Ultra-Massive-MIMO Systems

The conventional fully-digital implementation of massive-MIMO systems is not efficient due to the large required number of radio-frequency (RF) chains. To address this issue, hybrid analog/digital (A/D) beamforming was proposed and to date remains a topic of ongoing research. In this paper, we explore the hybrid A/D structure as a general framework for signal processing in massive and ultra-massive-MIMO systems. To exploit the full potential of the analog domain, we first focus on the analog signal processing (ASP) network. We investigate a mathematical representation suitable for any arbitrarily connected feed-forward ASP network comprised of the common RF hardware elements in the context of hybrid A/D systems, i.e., phase-shifter and power-divider/combiner. A novel ASP structure is then proposed which is not bound to the unit modulus constraint, thereby facilitating the hybrid A/D systems design. We then study MIMO transmitter and receiver designs to exploit the full potential of digital processing as well. It is shown that replacing the linear transformation in the digital domain with a generic mapping can improve the system performance. In some cases, the performance of optimal fully-digital MIMO systems can be achieved without extra calculations compared to sub-optimal hybrid A/D techniques. An optimization model based on the proposed structure is presented that can be used for hybrid A/D system design. Specifically, precoding and combining designs under different conditions are discussed as examples. Finally, simulation results are presented which illustrate the superiority of the proposed architecture to the conventional hybrid designs for massive-MIMO systems.

ВИСОКОЛІНІЙНІ БАЛАНСНІ ДВОТАКТНІ ПІДСИЛЮВАЧІ ПОСТІЙНОГО СТРУМУ ІЗ НИЗКОЮ ПОХИБКОЮ ЗСУВУ НУЛЯ

It is known that push-pull DC amplifiers (PPDA), as a rule, have a high linearity of the transfer characteristic, a wide passband (hundreds of MHz and GHz units) at the level of unity gain, and a significant rate of change in the output voltage (at least thousands of volts per microsecond). Serial models of such integrated PPDA are produced by Analog Devices, Texas Instruments, Linear Technology, National Semiconductor and others. Due to the presence of these characteristics, PPDA are widely used in current-voltage, current-current, ADC, DAC, direct digital synthesis systems and multi-channel digital systems for processing and recording analog signals. Despite the high indicated static and dynamic characteristics of the PPDAs built on bipolar transistors, which have a significant additive error in the form of an input zero bias current of hundreds of nA and μA units. Often this can degrade the static parameters of these devices and systems. When the input zero bias current appears, there are basic currents of bipolar transistors in the input stages of the amplifiers. To reduce their influence in single-cycle current amplifiers, some special circuit methods are used. Which allow an order of magnitude to reduce the input zero bias current of the differential stage without affecting the bias voltage or speed. To reduce the input zero bias current in the PPDA, it was proposed to apply basic current compensation in the input stages, as well as to build the input stages on Shiklai composite transistors, which will significantly improve the accuracy of the circuit as a whole.

Survey on Field Programmable Analog Array Architectures Eliminating Routing Network

This work focuses on reviewing the field programmable analog array (FPAA) architectures that eliminate the use of switches in signal path. The conventional FPAA architecture is composed of configurable analog blocks (CABs) connected together through switches in routing networks.The architectures covered in this survey have replaced the use of routing network by direct connection between CABs, and use of programmable analog building blocks. The first architecture covered is presented by Becker et al. with a hexagonal topology using operational transconductance amplifier (OTA) as a building block. The second architecture is presented by Mahmoud and Soliman, which uses the second generation current conveyor (CCII+) as a building block for their CABs arranged in a hexagonal architecture as well. Lastly, a more recent FPAA with a rectangular architecture proposed by Diab and Mahmoud is discussed, it uses the OTA as a building block for their rectangular architecture. The three FPAAs targeted continuous-time analog signal processing, having two architectures targeting high frequency applications, while the last targeting low frequency applications. The architectures, CAB structures, and the applications of each FPAA is covered separately in each section.

An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- γ band (80-160Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180nm CMOS process with 0.8V supply. This chip consumes 1.05 μW (0.205 μW for feature extraction only) power and occupies 0.245[Formula: see text] die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.

A 28 nm Bulk-CMOS Analog Front-End for High-Rate ATLAS Muon Drift-Tube Detectors.

This paper presents the design and experimental characterization of a 28 nm Complementary Metal Oxide Semiconductor (CMOS) Analog Front-End (AFE) for fast-tracking small-diameter Muon Drift-Tube (sMDT) detectors. The device exploits an innovative analog signal processing that allows a strong increase in the detection rate of events and significantly reduces the impact of fake/pile-up events, which often corrupt incident radiation energy events. The proposed device converts the input charge coming from incident radiations into voltage by a dedicated Charge-Sensitive Preamplifier (CSPreamp). Therefore, the fast-tracking concept relies on sampling the slope of the CSPreamp output voltage and using it for detecting both the incident event arrival instant and the amount of charge that has been effectively read out by MDT detectors. This avoids the long processing times intrinsically needed for baseline recovery transient, during which the detected signal can be severely corrupted by additional and unwanted extra-events, resulting in extra-charge (and thus in CSP output voltage extra-transient) during the signal roll-off. The proposed analog channel operates with a 5–100 fC input charge range and has a maximum dead-time of 200 ns (against the 545 ns of the state-of-the-art). It occupies 0.03 mm2 and consumes 1.9 mW from 1 V of supply voltage.

Parallel Signal Processing of a Wireless Pressure‐Sensing Platform Combined with Machine‐Learning‐Based Cognition, Inspired by the Human Somatosensory System

Inspired by the human somatosensory system, pressure applied to multiple pressure sensors is received in parallel and combined into a representative signal pattern, which is subsequently processed using machine learning. The pressure signals are combined using a wireless system, where each sensor is assigned a specific resonant frequency on the reflection coefficient (S11 ) spectrum, and the applied pressure changes the magnitude of the S11 pole with minimal frequency shift. This allows the differentiation and identification of the pressure applied to each sensor. The pressure sensor consists of polypyrrole-coated microstructured poly(dimethylsiloxane) placed on top of electrodes, operating as a capacitive sensor. The high dielectric constant of polypyrrole enables relatively high pressure-sensing performance. The coils are vertically stacked to enable the reader to receive the signals from all of the sensors simultaneously at a single location, analogous to the junction between neighboring primary neurons to a secondary neuron. Here, the stacking order is important to minimize the interference between the coils. Furthermore, convolutional neural network (CNN)-based machine learning is utilized to predict the applied pressure of each sensor from unforeseen S11 spectra. With increasing training, the prediction accuracy improves (with mean squared error of 0.12), analogous to humans' cognitive learning ability.

Spline-like Chebyshev polynomial model for compressive imaging

This paper introduces a novel spline-like parametric model for an image representation obtained directly from compressive imaging (CI) measurements. As a representation basis we use Chebyshev polynomials. To avoid common problem of blocking artifacts in block-based reconstruction algorithms, a desired number of derivatives are equated on the block boundaries in a spline-like fashion. This introduces a new set of constraints that fits into CI setup. Unlike splines, the proposed system of equations is underdetermined to provide a necessary degree of freedom for achieving sparsity by solving an ℓ1 optimization problem. Recovered coefficients of the parametric model can be further used for image processing where operations can be elegantly defined and calculated. This offers a new framework for acquisition and processing of analog signals without converting them into samples. Experiments on real measurements show that our model achieves sparse representation without visible blocking artifacts from a reduced set of CI measurements.

Time- and Frequency-Domain Characteristics of Direct-Detection Acousto-Optic Delay Lines

We discuss various details regarding the practical use of direct-detection acousto-optic delay lines, and develop a mathematical model for the input signal. An expression for the transient response was obtained and used to determine the acousto-optic delay line response to an boxcar input signal. This expression for the transient response was used to determine the cutoff frequency of the acousto-optic delay line and derive an equation for the impulse response to determine the acousto-optic transmission coefficient of the acoustooptic delay line as a function of frequency. The resulting equations are confirmed by numerical examples. The numerical results were in turn experimentally validated using the direct-detection acousto-optic delay line model developed in this paper. The theoretical and experimental results were compared using two criteria: the output response to a boxcar input signal and the cutoff frequency of the frequency response curve. The cutoff frequency was obtained using an oscillogram of the output pulse and the experimentally determined frequency response. A comparison of the theoretical and experimental results indicated that the time- and frequency-domain equations for the response curves have high potential for time-domain processing of broadband analog signals.

Nonlinear Loss Model in Absorptive-Type Ferrite Frequency-Selective Limiters

Absorptive-type ferrite-based frequency-selective limiters (FSLs) utilize nonlinear (NL) phenomena in magnetized ferrites to provide real-time analog signal processing of RF/microwave electromagnetic (EM) signals. There are no commercially available modeling tools that simulate these interactions, and the development and optimization of FSLs are largely done experimentally. FSL modeling and design is complicated by NL, multiscale, and multiphysics nature of operation. In this article, an NL loss model in a ferrite is proposed and implemented in an efficient numerical algorithm. The equivalent linear magnetic loss tangent is represented in a closed form. A full-wave numerical EM model with high-fidelity meshing is set up so that material properties are assigned to each mesh element and are iteratively adjusted depending on the local magnetic field. The numerical model is sliced along the EM wave propagation, and an NL eigenvalue is obtained for each slice as a function of frequency, power, and external magnetic bias field and stored in lookup tables. The slices are cascaded, and power attenuation is calculated with loss changing along the wave path according to the lookup tables. The resulting data are processed to be suitable for equivalent circuit models. Numerical results for coplanar waveguide FSL are validated by measurements. The proposed modeling approach is useful for engineering FSL devices.

Effects of Residual Hardware Impairments on Secure NOMA-Based Cooperative Systems

Non-orthogonal multiple access (NOMA) has been proposed as a promising technology that is capable of improving the spectral efficiency of fifth-generation wireless networks and beyond. However, in practical communication scenarios, transceiver architectures inevitably suffer from radio frequency (RF) front-end related impairments that cause non-negligible performance degradation. This issue can be addressed by analog and digital signal processing algorithms, however, inevitable aspects of this approach such as time-varying hardware characteristics and imperfect compensation schemes result to detrimental residual distortions. In the present contribution we investigate the physical layer security of NOMA-based amplify-and-forward relay systems under such realistically incurred residual hardware impairment (RHI) effects. Exact and asymptotic analytic expressions for the corresponding outage probability (OP) and intercept probability (IP) of the considered setup over multipath fading channels are derived and corroborated by respective simulation results. Based on this, it is shown that RHI affects both the legitimate users and eavesdroppers by increasing the OP and decreasing the IP. For a fixed OP, RHI generally increases the corresponding IP, thereby reducing the secure performance of the system. Further interesting insights are provided, verifying the importance of the offered results for the effective design and deployment of secure cooperative communication systems.

Использование учебно-методического комплекса «Электротехника»

The paper presents the laboratory practicum on electrical engineering and physics worked out on the basis of the teaching guide on electrical engineering including 5 test benches. 
 It includes 24 laboratory works with elements of independent research. The detailed and illustrated test benches of the training complex are the following: Electrical Engineering and Electronics, Electric Machines and Electric Drive, Electric Machine Assembly, Electric Energy, its Transmission and Quality, Principles of Electrical Safety. Some stands are connected to a software and hardware complex designed for measuring the studied values, reflection and processing of analog signals. The compactness and versatility of the training complex Electrical Engineering are noted; one can do 6–9 laboratory works on electrical engineering and physics at one stand. Mathematical calculations of the readings are recommended to perform in Mathcad computer algebra system. 
 A manual based on the laboratory works, which contains general safety rules, guidelines for per-forming tasks and requirements for their processing, is now under consideration. The advantages 
 of the elaborated laboratory workshop have been listed; the educational, developmental, pedagogical tasks for solving at the lesson have been analyzed; a laboratory work “Three-phase circuit connection in star scheme” is given as an example. The diagram of a star connection is presented; 
 a vector diagram of linear and phase voltages relations in a star connection is built. The oscillo-grams of currents under symmetrical load are illustrated. It has been noted that the individual tasks have an exploratory nature, they develop cognitive, independent and creative skills of students. The proposed methodological guidelines are recommended for specialists and bachelors in such areas as “Ship and Power Plants”, “Shipbuilding”, “Heat and Power Engineering and Heat Engineering”, etc., and can be used by teachers of general engineering disciplines

Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error

This paper studies multi-stage capacitive mixed-signal matrix-vector multiplying digital-to-analog (MDAC) conversion topologies for highly energy-efficient, high-resolution, and high-dimensional MIMO analog processing systems. In order to mitigate nonlinearity due to radix errors and capacitive mismatch encountered in compact low-power MDAC realizations, we introduce stochastic successive approximation , or S2A, as an online optimization algorithm for adaptive array analog signal processing amenable to efficient implementation in massively parallel mixed-signal hardware. S2A offers a direct alternative to stochastic gradient descent overcoming several of its shortcomings, such as its sensitivity to model error, while improving on the rate and quality of convergence. S2A overcomes non-convergence typically encountered with gradient descent for non-convex optimization landscapes induced by a mismatch in capacitive multiplying digital-to-analog converter components when applied to adaptive analog signal processing. Experimental validation of S2A in mixed-signal hardware for real-time RF adaptive beamforming demonstrates 65 dB of over-the-air, multipath interferer suppression in fewer than 25 S2A iterations.

Development of A Low-Cost Arduino-Based 12-Lead Ecg Acquisition System And Accompanied Labview Application

In this paper, the design of a real-time digital multi--channel ECG signal acquisition system is presented. With the purpose of fabrication towards a simple, compact and low-cost tool for bioelectrical signal processing laboratories, the system is developed to acquire the 12 leads EGC signals and converted to numerical data based on an Arduino module named as Leonardo equipped 12 channels ADC. To observe the EGC waves, the ECG signals are amplified through designed amplifiers with the gain of 60 dB. To reduce the effects from the DC component as well as the baseline wandering and the high frequency noise, the active analog bandpass filter ranged in 0,05 Hz to 100 Hz was designed. The power line noise of 50 Hz also decreased with an active analog bandstop filter with attenuation -38 dB. Under the PC application was built using Labview programing, the low-cost digital ECG signal acquisition system was demonstrated with the requirement of observation in real-time. To clarify the small wave in the digital EGG signal, the limitation of the analog signal processing is improved through the digital filters parameterized in the software to increase the SNR from 1.4 dB to 27.6 dB. Practically, the system is evaluated through a series of experiments on a volunteer person resulting the ECG data is recorded and stored in a TDMS file. Since the system is designed as opened-system, a series of developments towards various applications in biomedical diagnosis based on digital signal analysis techniques is promised to be feasible in the near future.

Design of 4-Channel Photoelectric Transceiver System-in-Package for Next Generation Radar Applications

This paper introduces a four-channel photoelectric transceiver system-in-package. It has four-channel digital photoelectric transceiver, analog IF transceiver and signal processing functions. It integrates four-channel optical module, four-channel parallel ADC, four-channel synchronous DDS, static random access memory, two Falsh memories, crystal oscillator and NTC thermistor. Structurally, the ceramic integrated shell is used for high density integration, and its volume is less than 40 mm x 40 mm x 6 mm. The test results show that the bit error rate is 6.36E-13 at 6.25Gbps data rate, and the eye diagram is normal.

Design of a Floating Gate Synapse Simulation Model

Proposing a simulation model of Floating-gate (FG) MOSFET whose characteristics when operated at sub-threshold conduction are like a synapse of brain. It can store, program, and adapt information (charge). The model consists of empirical equations and its parameter values have been extracted from fabricated results. The post fabrication programming of charge at the FG have been observed using two quantum-controlled processes (Fowler Northeim tunneling & hot electron injection) with the help of externally applied voltages, which in turn program FGMOS characteristics like threshold voltage, Vth. The programming is non-volatile and stable with changing temperature (4μV/°C) and noise. The Vth programming range is varied by more than 7V to 8V of its original value with very high bit (about 13-bit) of programming precision/resolution. The model layout/mask consume maximum of 130×90 μm2 of chip area and average power consumed by model is around 0.315mW. This verified FG simulation model can introduce the concept of on-chip tuning ability, programming ability, reconfiguring ability in precision analog signal processing designs like inductor, filters, controller circuits, voltage-controlled oscillators, etc. On adding adequate feedback mechanism to FGMOS model, it shows self-adaption of FG charge, which can be used to emulate features of a neuron/synapse in CMOS based neuromorphic circuits emulating several cognitive behaviors of human brain like Winner takes all circuits, circuits generating spikes (STDP), etc.

ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm

The scale-invariant feature transform (SIFT) algorithm is still one of the most reliable image feature extraction methods. Despite its excellent robustness on various image transformations, SIFT’s intensive computational burden has been severely preventing it from being used in real-time and energy-efficient embedded machine vision systems. To reduce processing time and energy cost while executing SIFT, an analog signal processing architecture, analog signal processing (ASP)-SIFT, is proposed in this article. In ASP-SIFT, the Gaussian pyramid construction, difference-of-Gaussian (DoG) pyramid construction and keypoint locating, which are the primary steps of the keypoint detection part of the SIFT algorithm, are done directly with analog circuit networks. Thus, by completing keypoint detection in the analog domain, the total processing time is approximately equal to the settling time of the circuit network. Besides, by adopting a current-mode circuit network operating in the subthreshold region, the power dissipation would be very low. Simulation results show that the total processing speed for a typical video graphics array (VGA)-format ( $640\times480$ ) image is up to 2.3 kframes per second, which is at least $3.26\times $ faster than the state-of-the-art digital hardware accelerators, while the system power is 94.5 mW and the energy consumption is only $40~\mu \text{J}$ per frame.

42.2:Invited Paper:Multi‐Force Touch Technology Augmenting Capacitive Touch in Displays

This paper presents a new multi‐force touch technology that augments standard capacitive touch sensing in flat panel, and potentially flexible, displays. It uses an augmented approach and yields both location and force in a single‐signal, which is then separated and conditioned using unique analog and digital signal processing algorithms. Location‐by‐force is intrinsic to this newUltraTouchtechnology, thus enabling stylus‐independent, under‐water interactivity. In view of the simplicity in stack‐up architecture, the technology is compatible to roll‐to‐roll touch panel production lines, scalable to large areas, and importantly, low in cost.

Controlling acoustic waves using magneto-elastic Fano resonances

We propose and analyze theoretically a class of energy-efficient magnetoelastic devices for analog signal processing. The signals are carried by transverse acoustic waves while the bias magnetic field controls their scattering from a magnetoelastic slab. By tuning the bias field, one can alter the resonant frequency at which the propagating acoustic waves hybridize with the magnetic modes, and thereby control transmission and reflection coefficients of the acoustic waves. The scattering coefficients exhibit Breit-Wigner/Fano resonant behavior akin to inelastic scattering in atomic and nuclear physics. Employing oblique incidence geometry, one can effectively enhance the strength of magnetoelastic coupling, and thus countermand the magnetic losses due to the Gilbert damping. We apply our theory to discuss potential benefits and issues in realistic systems and suggest routes to enhance the performance of the proposed devices.

On-chip wavefront shaping with dielectric metasurface

Metasurfaces can be programmed for a spatial transformation of the wavefront, thus allowing parallel optical signal processing on-chip within an ultracompact dimension. On-chip metasurfaces have been implemented with two-dimensional periodic structures, however, their inherent scattering loss limits their large-scale implementation. The scattering can be minimized in single layer high-contrast transmitarray (HCTA) metasurface. Here we demonstrate a one-dimensional HCTA based lens defined on a standard silicon-on-insulator substrate, with its high transmission (<1 dB loss) maintained over a 200 nm bandwidth. Three layers of the HCTAs are cascaded for demonstrating meta-system functionalities of Fourier transformation and differentiation. The meta-system design holds potential for realizing on-chip transformation optics, mathematical operations and spectrometers, with applications in areas of imaging, sensing and quantum information processing.

Method of frequency-phase detection used in ADC based on PLL circuit

The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.