Analog Signal Processing Circuits Research Articles

A New CMOS FTFNDITA Implementation and Its Application

ABSTRACT This research article presents a new design of a CMOS analog building block, termed a Four Terminal Floating Nullor Differential Input Transconductance Amplifier (FTFNDITA). This new analog building block can operate up to the MHz range and offers low-power dissipation circuitry. The proposed FTFNDITA works with ± 1.65 V power supply. Moreover, a ICs-based FTFNDITA is also developed using an off-self commercially available Current Feedback Operational Amplifier (CFOA) as IC AD844 and Operational Transconductance Amplifier (OTA) as IC LM13700 or IC CA3080. To extend the application perspective of the proposed FTFNDITA blocks, a few fundamental analog signal processing circuits like the design of Floating Inductor Simulator (FIS), First-Order Low-Pass Filter (FLPF), Floating Capacitance Multiplier (FCM), and its extension for active filter design, are incorporated. In addition, a non-ideality investigation is also performed to test the deviation between the ideal and practical design. Finally, PSPICE and experimental verifications are observed to validate the functionality of FTFNDITA.

Flexi-EIT: A Flexible and Reconfigurable Active Electrode Electrical Impedance Tomography System.

Electrical Impedance Tomography (EIT) systems have shown great promise in many fields such as real-time wearable healthcare imaging, but their fixed number of electrodes and placement locations limit the system's flexibility and adaptability for further advancement. In this article, we propose a flexible and reconfigurable EIT system (Flexi-EIT) based on digital active electrode (DAE) architecture to address these limitations. By integrating a reconfigurable number of up to 32 replaceable DAEs into the flexible printed circuit (FPC) based wearable electrode belt, we can enable rapid, reliable, and easy placement while maintaining high device flexibility and reliability. We also explore hardware-software co-optimization image reconstruction solutions to balance the size and accuracy of the model, the power consumption, and the real-time latency. Each DAE is designed using commercial chips and fabricated on a printed circuit board (PCB) measuring 13.1 mm × 24.4 mm and weighing 2 grams. In current excitation mode, it can provide programmable sinusoidal current signal output with frequencies up to 100 kHz and amplitudes up to 1 mA p-p that meets IEC 60601-1 standard. In voltage acquisition mode, it can pre-amplify, filter, and digitize the external response voltage signal, improving the robustness of the system while avoiding the need for subsequent analog signal processing circuits. Measured results on a mesh phantom demonstrate that the Flexi-EIT system can be easily configured with different numbers of DAEs and scan patterns to provide EIT measurement frames at 38 fps and real-time EIT images with at least 5 fps, showing the potential to be deployed in a variety of application scenarios and providing the optimal balance of system performance and hardware resource usage solutions.

Design of Low Power Analog/RF Signal Processing Circuits Using 22 nm Silicon-on-Insulator Schottky Barrier Nano-Wire MOSFET

The gate-all-around (GAA) silicon-on-insulator (SOI) Schottky barrier (SB) nano-wire (NW) MOSFET was recently proposed for low-power and high-frequency analog and radio frequency (RF) circuits. But their use in low-power and high-frequency analog/RF circuits is still under investigation. In this work, basic analog signal processing circuits using gate-all-around SOI-SB-NW MOSFETs are designed for low-power and high-frequency applications. These basic and necessary analog processing circuits are designed for ± 0.3 V and ± 0.25 V power supplies to work on frequencies up to 10 GHz. The analog/RF characteristics of the GAA SOI-SB MOSFET are compared with those of the GAA SB NW MOSFET. The SOI-SB NW MOSFET shows improvements in early voltage, output resistance, and transconductance generation factor. The Silvaco TCAD simulator is used to obtain the results and perform numerical simulations. Simulation results show good analog/RF performance of the analog processing circuits.

A Compact and Ultra-Low-Power Low-Pass Filter Based on Band-to-Band Tunneling Effect

Continuous-time filters with low-frequency cutoff are crucial building blocks in analog signal processing circuits for speech processing and biomedical applications. The design of an integrated continuous-time filter with a cutoff frequency spanning from sub-Hz to a few kHz is constrained by the ultra-low power and area minimization requirement. In this article, we have experimentally demonstrated a low pass filter response using only a single partially depleted (PD) silicon on insulator (SOI) transistor. The proposed novel filter is based on band to band tunnelling (BTBT). This low pass filter is on-chip tunable to provide a wide cutoff frequency ranging from 2 Hz to 20 kHz, with a silicon footprint of 9 μm2 and the maximum power consumption of 0.6 nW in Global Foundries’ (GF) 45 nm RFSOI technology. The proposed tunneling-based filter is less prone to process variations and mismatches as compared to traditional integrated analog filters. The proposed BTBT-based passive RC filter with spurious free dynamic range (SFDR) of 29 dbc, outperforms previously reported filters in the literature in terms of power consumption and area. The ultra-low power consumption and area efficiency make this proposed low pass filter suitable for the multichannel analog front-end low-frequency filters for noise-tolerant neural network-based applications such as speech recognition and electrophysiological signal recognition.

Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification

To address the power and area bottleneck imposed by the frontend feature extractor relative to the backend neural network in on-device keyword spotting (KWS), we propose two time-mode analog signal processing (ASP) circuit techniques showcased in an analog audio feature extractor chip that advances the state of the art in power- and area-efficiency. Time-mode analog filterbank interpolation uses digital XOR gates to double the number of outputs of an analog bandpass filterbank. Time-mode analog rectification uses a single digital XOR gate as an analog full-wave rectifier. The 65 nm low power (LP) CMOS chip uses only 80 nW and 0.53 mm2 to extract from an input analog audio signal, an output digital auditory feature vector with 31 elements. This represents <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$18\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3\times $ </tex-math></inline-formula> improvements in power/feature and area/feature, as compared, respectively, to the most area- and power-efficient published analog audio feature extractor chips. All the while, competitive classification accuracy is maintained at >90% across ten keywords, as evaluated by feeding the chip’s digital output directly into a small-footprint software backend classifier.

Design of Rogowski Switch-Current Sensor With Offset Compensation for Three-Phase SiC Inverter

This article proposes a Rogowski switch-current sensor (RSCS) with the offset compensation for the current control of the three-phase SiC inverter. The RSCS is built into the four-layer print circuit board (PCB) gate drive board. The coil parameters are analyzed with the Ansys software (Maxwell and Q3D) and then compared with the measurement results. The analog signal processing circuits are implemented with the operational amplifier (op amp) to reconstruct the switch current and the phase current. Unfortunately, the RSCS suffers from the op amp offset voltage and bias current integration, which varies according to the duty cycle and switching frequency. This article proposes an offset compensation software (S/W) to address this issue. Moreover, an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> discharge factor is proposed to make up for the discharging phenomenon of the capacitor in the integrator feedback path. A three-phase SiC inverter prototype is built and tested with the three-phase inductor load to verify the feasibility of the method. Experimental results at 10–30 kHz, 600 V, 150 A show the proposed method to have less than 2% sensing error.

Application of Voltage Difference transconductance Amplifier (VDTA) for realization of analog active filter: Review

The paper reviews the published work for realization of analog signal processing circuits especially filters using VDTA as an active building block. VDTA is new active building block which has been used to realize the filters and other analog signal processing networks. Important advantage of ideal effects of VDTA is also presented. Moreover, various types of active filters employing VDTA is its electronic tuning of transconductance gain. At the outset of this review paper brief account of filters and their application is given. Detailed study including Non-VDTA is also presented.

Optimal Long Distance ECG Signal Data Delivery Using LoRa Technology

Cardiovascular disease is the leading cause of death in the world and the number one killer in Indonesia, with a mortality rate of 17.05%. The target of this research is to increase the range of electrocardiograph (ECG) equipment using LoRa Technology. With LoRa Technology, it is expected that the data transmission process can run effectively and produce an accurate ECG signal and minimal noise. The research method is by sending a heart signal from the ECG simulator by the microcontroller via LoRa Technology which is received by the PC (Personal Computer) and the ECG signal is displayed on the PC display. The most optimal setting will be obtained from the sender-receiver distance and baudrate by measuring data loss and delay. In this study, the simulated cardiac signal from the phantom ECG is fed to an analog signal processing circuit, then the signal is converted to digital and digitally filtered on the microcontroller, then the signal is sent via the LoRa HC-12 Transceiver to a PC with baudrate, distance and barrier settings. The results obtained are that data transmission can be carried out at a distance of 175 meters without a barrier and a distance of 50 meters with a barrier. This remote ECG equipment can detect heart signals and the results can be sent to a PC using LoRa Technology. The implication is that the transmission of ECG signal data via the Lora HC-12 Transceiver media can be carried out optimally at the 9600 baudrate setting.

Close-Loop Current Control With Current-Sensing Resistor for Electromagnet Driven by Full-Bridge PWM Inverter

The full-bridge pulse-width-modulation (PWM) inverter is wildly applied to drive the electromagnet and enables advanced technologies, such as the active magnetic bearing (AMB) and the permanent-electro magnetic suspension (PEMS). However, the characteristic relationship between the current through the electromagnet and the duty cycle of the PWM signal has strong nonlinearity around the zero current. Moreover, the electromagnet possesses the induction that results in the time constant and significantly hinders the change of the current. Hence, the open-loop control of the full-bridge PWM inverter cannot accurately or timely tune the current through the electromagnet, especially around the zero current. This work proposes a closed-loop current control approach by three steps: (1) inserting a current-sensing resistor into the middle of the electromagnet, (2) obtaining the current signal with an analog signal-processing circuit, and (3) generating the PWM signal with the bang-bang control circuit. The proposed approach innovatively arranges the current-sensing resistor to take advantage of the symmetry and to minimize the influence from the high-frequency switching of the inverter, so that the measured current signal is comparable to the hall-effect current sensor. The experimental results demonstrate the effectiveness and efficiency of the proposed closed-loop current control approach, though the weak charging capability of the full-bridge PWM inverter still hinders its performance.

A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}$ </tex-math></inline-formula> of 190 GHz in typical operating conditions and packaged in a 5-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

Evaluation of Ionizing Radiation Effects on Device Modules Used in Wireless-Based Monitoring Systems

To increase the reliability of wireless-based monitoring systems under ionizing radiation environments, multiple diversified commercial off-the-shelf (COTS) modules have been used to achieve radiation tolerance. This paper presents experimental results of radiation tests on key modules in wireless-based monitoring systems, which include analog signal processing circuits, analog-to-digital converter (ADC) modules, microcontroller modules, and wireless transmission modules. In total, 12 modules have been evaluated, (i.e. 3 analog modules, 3 ADCs, 3 microcontrollers, and 3 wireless transmission modules). The radiation tests are conducted using the gamma radiator at The Ohio State University Nuclear Reactor Lab (OSU-NRL). The performance parameters of these 12 modules are investigated under high dose rate (20 krad(Si)/h). Experimental results have shown that the tested modules perform satisfactorily with little sign of degradation until the total dose levels reach the tolerable limits for these modules. Experimental results support the fact that, by using diversified COTS components, one may be able to achieve equivalent performance as those built by using radiation-hardened components, but with a considerable cost-saving. Furthermore, the tests also show that digital modules, particularly, with higher speed processors (i.e. microcontrollers) may be more susceptible to radiation than other types of modules. Therefore, additional shielding should be used to protect them.

Single-Event Effects in Pinned Photodiode CMOS Image Sensors: SET and SEL

Single-event transient (SET) and single-event latchup (SEL) of a 4T pinned photodiode (PPD) complementary metal&#x2013;oxide&#x2013;semiconductor (CMOS) image sensor (CIS) fabricated with a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process were investigated using heavy ions and a picosecond pulsed laser. The SET bright spot characteristics were further studied, and the transient bright spots formed by laser and heavy ions were analyzed. The sensor exhibited SELs and micro-SEL. To determine the precise sensitive location where SEL occurred in the CIS, a pulsed laser with a 2-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> beam spot was used to scan the entire surface of the device. The results revealed that SEL occurred in the peripheral circuits of the CIS, including the analog signal processing circuit, row-addressing circuit, and analog-to-digital conversion (ADC). The cross section of the SELs for the sample were measured using a linear energy transfer (LET) ranging from 8.62 to 81.35 MeV<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm² mg^&#x2212;1. The SEL rates in space for the used CIS were predicted using the CREME96 tool.

Fractional derivative of logarithmic function and its applications as multipurpose ASP circuit

This paper presents a new approach to approximate the fractional order derivative of a logarithmic function using the Caputo definition. Further, this approximated fractional derivative has been used to conceptualize and design a multipurpose ASP (analog signal processing) circuit, by cascading the logarithmic amplifier with fractional order differentiator. The proposed multipurpose ASP circuit is capable to generate different kinds of signals (such as step signals with controlled amplitude, tangent and cotangent signals with controllable fractional power) for different inputs. Moreover, this circuit is also helpful to develop reciprocal, square root, cube root and nth-root of the input signal, up to some extent. Several types of input signals have been taken into consideration and the corresponding output responses are obtained by varying the order of differentiation in fractional sense. Numerical as-well-as circuit simulations have been done in MATLAB and PSpice environments to validate the theoretically obtained results. Further, hardware implantation has also been done to see the practical aspects of the proposed design.

A Novel Fingerprint Sensing Technology Based on Electrostatic Imaging.

In this paper, we propose a new fingerprint sensing technology based on electrostatic imaging, which can greatly improve fingerprint sensing distance. This can solve the problem of the existing capacitive fingerprint identification device being easy to damage due to limited detection distance and a protective coating that is too thin. The fingerprint recognition sensor can also be placed under a glass screen to meet the needs of the full screen design of the mobile phone. In this paper, the electric field distribution around the fingerprint is analyzed. The electrostatic imaging sensor design is carried out based on the electrostatic detection principle and MEMS (micro-electro-mechanical system) technology. The MEMS electrostatic imaging array, analog, and digital signal processing circuit structure are designed. Simulation and testing are carried out as well. According to the simulation and prototype test device test results, it is confirmed that our proposed electrostatic imaging-based fingerprint sensing technology can increase fingerprint recognition distance by 46% compared to the existing capacitive fingerprint sensing technology. A distance of more than 439 μm is reached.

Analog and digital signal processing method using multi-time-over-threshold and FPGA for PET.

The goal of this study was to develop an analog and digital signal processing method using multi-time-over-threshold (MTOT) and field programmable gate arrays (FPGAs) to extract PET event information by using the internal clock of FPGA (~350 MHz), without ADC and TDC. The PET detector modules were composed of a 4 × 4 matrix of 3 × 3 × 20 mm3 LYSO and 4 × 4 SiPM array. Output charge signals of PET detector modules were amplified and fed into four comparators to generate trigger signals. The energy of the detected gamma ray was calculated by integrating the digitized pulse and the arrival time was determined from the time stamp of the lowest trigger signal by FPGA. The data packet containing energy, time, and position information was stored in list mode on the host computer. The performance of analog and digital signal processing circuits using MTOT method and FPGA was evaluated by measuring energy and time resolution of the proposed method and the values were 19% and 900 ps, respectively. This study demonstrated that the proposed MTOT method consisting of only FPGA without ADC and TDC could provide a simple and cost-effective analog and digital signal processing system for PET.

A multi-channel high-speed magnetic field detection system based on FPGA for transcranial magnetic stimulation.

Transcranial magnetic stimulation (TMS), a popular technology, acts on the brain by using a pulse magnetic field to cause a series of physiological and biochemical reactions. In order to detect the magnetic field generated by the TMS coil with high-speed and multi-channel performance, a novel magnetic field detection system based on a field programmable gate array (FPGA) is designed and implemented. The detection system includes an induction coil array, a data acquisition (DAQ) card, and upper computer monitor software. The DAQ card contains analog signal processing circuits, a multiplexer, an analog-to-digital converter, and a FPGA with a high-speed, parallel, and switching idea. The system can sample at a rate of 500 ksps, with 14-bit resolution and 12 channels. The three dimensional (3D) magnetic field can be monitored on the screen with a waveform display and 3D magnetic field vector display. The DAQ card has a good signal noise and distortion and cross talk of 88.35 dB and -79.69 dB, respectively. Compared with the NI DAQ card, the proposed system has a relative error smaller than 1.81% and a mean square error smaller than 2.89 × 10-6, which verifies that the proposed detection system has a good performance. The multi-channel high-speed magnetic field detection system provides an important platform for the study of TMS in medical, engineering, and other fields.

Real-time emulation of block-based analog circuits on an FPGA

In order to provide a real-time emulation platform for analog signal processing circuits, we propose a block based approach with a constant worst case runtime. We evaluate an FPGA-based implementation of this approach by comparing its output for different test cases to a non-real-time SPICE simulation. The implementation runs at a sampling rate of 88.2 kHz and features roundtrip times as low as 0.096 ms (12 bit ADC) and 0.190 ms (16 bit ADC). A completely automated process is introduced for fitting model parameters of filters and various nonlinear blocks. The fitting process is evaluated based on 35 block examples with R2 values ranging from 0.967 to 0.999. For complex filter structures we were able to replicate the frequency responses predicted by a SPICE AC analysis accurately. Furthermore we compare measured transient responses of the FPGA-based emulation with SPICE and discuss advantages and disadvantages of the approach.

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

A 4-channel Time Interleaved Sampler based 3-5 GHz band CMOS Radar IC in 0.13 mm for Surveillance

This paper presents a 3-5 GHz band CMOS UWB radar IC realized in a 0.13 mm CMOS technology for surveillance. Sampling resolution and detectable range of the proposed IC are determined to be 3 cm and 15 m, respectively, to serve a surveillance function. To reduce the scan time while satisfying resolution and detection range, equivalent time sampling and a 4-channel time interleaved sampler are used. The DC offset mismatch in the 4-channel receiver is greatly reduced via a DC offset compensation and BJT-based op-amp for analog signal processing (ASP) circuits. Measurement results show that the center frequency and bandwidth of the pulse can be adjusted in the range of 3 GHz - 5 GHz and 0.5 GHz - 2 GHz, respectively. The measured range for human target is up to 11 m. The chip size is 4 mm ´ 2.5 mm, and 81 mA (transmitter) and 38 mA (receiver) are consumed at 1.5 V supply.