Analog Readout Circuit Research Articles

Optimized register level transfer mechanism for ASIC-based memscomputing

Micro-electromechanical system-based semiconductor sensor systems typically need a reliable on-chip analog readout circuit to identify and process changes in physical properties. To improve the mobility, robustness, reliability and performance (in terms of power consumption and speed) of the sensor system, the remaining parts of the post-processing logic, such as the digital data processor (or part of it), can also integrated into the chip. Cost and integration are always important considerations in both analog and digital designs, but they become even more important; the subsystem of data processing must be squeezed into a very small space near the structure of the micro-electromechanical system (MEMS) sensor. The paper introduces a new Buffalo-based register-transfer level (BRTL) method that aims to improve the efficiency and reliability of the system of digital data processing for MEMS sensor post-processing algorithm. Initially, the memcomputing system was designed with the needed functional processing elements. Then, a novel Buffalo-based register-transfer level design is modelled in the MEMS architecture. The digital data transmission process is performed to estimate the reliability of the proposed BRTL model. Finally, the performance of the proposed model can be validated.

A fully differential analog read-out circuit for differential capacitive sensors

A fully differential analog read-out circuit for differential capacitive sensors

An Analog Readout Circuit With a Noise-Reduction Input Buffer for MEMS Microphone

This brief presents a programmable-gain analog readout circuit with a noise-reduction input buffer for single-ended micro-electro-mechanical-system (MEMS) microphone sensors, aiming at applications requiring low cost and high SNR. An internal feedback path is adopted in the source-follower-based input buffer to suppress the noise contribution from its bias circuit, while improve the linearity and power supply rejection ratio (PSRR). In addition, another feedback path taking advantage of the readout circuit’s high-voltage bias output for the MEMS sensor is employed to realize an effective gain of larger than unity for the input buffer, which can suppress the noise contribution of the programmable capacitive-feedback preamplifier. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology, the proposed readout circuit achieves a 3.7- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> Vrms (A-weighted) input-referred noise. After packaged with a commercial MEMS microphone sensor, the overall system achieves an A-weighted SNR of 66 dBA, an acoustic overload point (AOP) of 119.5 dB sound pressure level (SPL) and a PSRR of 68 dB@1kHz. The readout chip consumes 115 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> under a 2-V power supply and occupies an active area of 0.25mm2.

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. The measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

Motion Artifact Removal Techniques for Wearable EEG and PPG Sensor Systems

Removal of motion artifacts is a critical challenge, especially in wearable electroencephalography (EEG) and photoplethysmography (PPG) devices that are exposed to daily movements. Recently, the significance of motion artifact removal techniques has increased since EEG-based brain–computer interfaces (BCI) and daily healthcare usage of wearable PPG devices were spotlighted. In this article, the development on EEG and PPG sensor systems is introduced. Then, understanding of motion artifact and its reduction methods implemented by hardware and/or software fashions are reviewed. Various electrode types, analog readout circuits, and signal processing techniques are studied for EEG motion artifact removal. In addition, recent in-ear EEG techniques with motion artifact reduction are also introduced. Furthermore, techniques compensating independent/dependent motion artifacts are presented for PPG.

High-Linearity High-Resolution Time-of-Flight Linear-Array Digital Image Sensor Using Time-Domain Feedback.

This paper presents a high-linearity high-resolution time-of-flight (ToF) linear-array digital image sensor using a time-domain negative feedback technique. A coarse ToF measurement loop uses a 5-bit digital-to-time converter (DTC) and a delayed gating-pulse generator for time-domain feedback to find the zero of the difference between ToF and the digital estimate of the gating-pulse delay while maintaining a constant operating point of the analog readout circuits. A fine ToF measurement uses a delta-sigma modulation (DSM) loop using the time-domain feedback with a bit-stream signal form. Because of the self-contained property of the DSM for low distortion and noise exploited by the oversampling signal processing, the proposed technique provides high-linearity and high-range resolution in the fine ToF measurement. A prototype ToF sensor of 16.8 × 16.8 μm2 two-tap pixels and fabricated in a 0.11 μm (1P4M) CMOS image sensors (CIS) process achieves +0.9%/−0.47% maximum nonlinearity error and a resolution of 0.24 mm (median) for the measurement range of 0–1.05 m. The ToF sensor produces an 11-bit fully digital output with a ToF measurement time of 22.4 ms.

Design and Characterization of the CLICTD Pixelated Monolithic Sensor Chip

A novel monolithic pixelated sensor and readout chip, the compact linear collider tracker detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the compact linear collider (CLIC) and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of $16\times 128$ elongated channels, each measuring $300\times 30\,\,\mu \text {m}^{2}$ . Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit time-of-arrival (with 10 ns time bins) and 5-bit time-over-threshold measurement is performed on the combined digital output of the 8 subpixels in every channel. The chip has been fabricated in two process variants and characterized in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e− and a noise of about 14 e− rms. The design aspects and characterization results of the CLICTD chip are presented.

An Analog Interface Circuit for Capacitive Angle Encoder Based on a Capacitance Elimination Array and Synchronous Switch Demodulation Method.

This paper presents an analog interface application-specific integrated circuit (ASIC) for a capacitive angle encoder, which is widely used in control machine systems. The encoder consists of two parts: a sensitive structure and analog readout circuit. To realize miniaturization, low power consumption, and easy integration, an analog interface circuit including a DC capacitance elimination array and switch synchronous demodulation module was designed. The DC capacitance elimination array allows the measurement circuit to achieve a very high capacitance to voltage conversion ratio at a low supply voltage. Further, the switch synchronous demodulation module effectively removes the carrier signal and greatly reduces the sampling rate requirement of the analog-to-digital converter (ADC). The ASIC was designed and fabricated with standard 0.18 µm CMOS processing technology and integrated with the sensitive structure. An experiment was conducted to test and characterize the performance of the proposed analog interface circuit. The encoder measurement results showed a resolution of 0.01°, power consumption of 20 mW, and accuracy over the full absolute range of 0.1°, which indicates the great potential of the encoder for application in control machine systems.

Evaluation of Hamamatsu H13974 Large Sensitive Area Flat Panel PMT Array for Use in Small Animal Imaging and Scintimammography

In this paper, we report for the first time on the performance of the Hamamatsu H13974 flat panel photomultiplier tube (PMT) array. This new photodetector is based on four Hamamatsu H12700A position sensitive PMTs in a $ 2 \times 2$ arrangement providing large sensitive area ( $ {100\times 100}$ mm2) for use in scintimammography or/and medium size mammals imaging. We acquired raw images from three pixellated scintillators for possible positron emission tomography and single photon emission computed tomography applications (BGO with $ {2\times 2\times 6}$ mm3, CsI:Tl with $ {2\times 2\times 4}$ mm3, and CsI:Na with $ {1.45\times 1.45\times 6}$ mm3 pixel sizes) irradiated with 511 keV (68Ga) and 140 keV (99 m Tc), respectively. Different coupling schemes involving optical grease and optical glasses of different thicknesses were used in order to find the scheme that better resolves the crystal elements of the scintillators especially in the dead areas of the flat panel PMT array. We present the results of investigating the basic properties, including energy resolution, intrinsic spatial resolution, detection efficiency, and sensitivity uniformity. The scintillation material, the coupling scheme and the analog readout circuits are the main factors that affect the performance of the detector. The proper combination of these factors should be carefully chosen so as to build a high performance imaging system.

A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End

A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- $\mu{\rm m}$ CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 $\mu{\rm W}$ and 50 $\mu{\rm T}$ , respectively.

Compact CMOS Analog Counter for SPAD Pixel Arrays

In this brief, the design and experimental characterization of a compact analog readout circuit for photon counting is presented. A test chip, including a 20 × 20 counter array, has been manufactured in a standard 0.35-μm CMOS technology. The circuit delivers an output voltage proportional to the input pulse count, with a programmable voltage step. The counting resolution can be set to 7 or 8 bits with a readout noise of 0.15 and 0.3 electrons, respectively, and an output nonuniformity of 4% across the array, which brings a factor 3 improvement with respect to previous analog designs. A worst case integral nonlinearity of ±0.6 and ±1 LSB and a differential nonlinearity of ±0.3 and ±0.6 LSB were measured over the whole array of counters at 7- and 8-bit resolution, respectively. The area occupation of this analog implementation (230 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) is a factor 10 smaller than a digital counter of the same resolution. Due to the compactness and the lower counter power consumption with regard to the former designs, the proposed circuit can be exploited for signal processing in high-spatial resolution single-photon-avalanche-diode-based image sensors.

The front-end chip of the SuperB SVT detector

The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.

A low‐power integrated electronic nose system

PurposeThe purpose of this paper is to present a novel approach for fabricating electronic nose (e‐nose) systems for adaptation into autonomous wireless sensor nodes. Such systems must fulfill a combination of requirements that currently cannot be met by existing technologies. The paper also contains an overview of the various application domains that are envisaged for such miniaturized electronic nose systems.Design/methodology/approachThe approach makes use of micromechanical systems that are an ideal technology for fabricating miniaturized sensor arrays for low‐power applications. An array of doubly clamped micromechanical beams with integrated piezoelectric transducers is presented.FindingsThe presented approach fulfills the requirements of sensitivity, arrayability, integratability and low‐power operation.Research limitations/implicationsFurther research is required to integrate the structures with low‐power analog readout circuits and to demonstrate simultaneous measurements from multiple structures.Practical implicationsThe presented technology makes use of established micromachining techniques and deploys commercial inkjet printing for functionalization of the individual detection elements. This enhances its potential adaptation by industry.Originality/valueThe innovative concept paves the way for autonomous electronic nose systems.

A Novel Analog Autocalibrating Phase-Voltage Converter for Signal Phase-Shifting Detection

In this study, we present a novel analog read-out circuit, operating a phase-voltage conversion, suitable for the detection of signal phase shifting for micro- and nano-sensor system applications. Its main characteristics are the following: good linearity in the considered phase-shift range, capability of phase sign detection, independence from input signal amplitudes, setting and zeroing of the offset, autocalibration, high sensitivity and resolution, and high accuracy and precision. For these reasons and, in particular, thanks to its simple internal topology, the developed circuit can be considered as a suitable analog interface for portable measurement systems. Experimental results, achieved through a laboratory breadboard and using sample signals, have confirmed, with respect to the other solutions reported in literature, better linearity, higher sensitivity (equal to about 37 mV/degree in the ±90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> phase-shift range) and resolution (lower than 0.1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> in the same phase-shift range) for both positive and negative phase variations. When a more reduced phase-shift range must be detected (i.e., for optical sensor applications), it is possible to set the circuit parameters to further increase sensitivity and resolution.

Body effect minimization using single layer structure for pH-ISFET applications

In this study, the hafnium oxide (HfO 2) thin film deposited by using radio frequency (r.f.) sputter was used as the sensing membrane of ion sensitive field-effect transistor (ISFET) for pH detection. For low cost and easy fabrication, the single HfO 2 gate ISFET without SiO 2 as buffer layer have been developed to compare with the conventional ISFETs with HfO 2 or Si 3N 4 on SiO 2 buffer layer in same process. Electrical characteristics including off current, transconductance, subthreshold swing and body effect of metal–insulator–semiconductor field-effect transistor (MISFET) devices and pH sensing properties including sensitivity, linearity, drift coefficient and body effect of ISFET devices were investigated in detail. The single HfO 2 gate MISFET exhibits better electrical performance like higher transconductance, smaller subthreshold swing and lower body effect than the stack HfO 2/SiO 2 gate MISFET and Si 3N 4/SiO 2 gate MISFET. In pH sensing properties, both the single HfO 2 gate ISFET and the stack HfO 2/SiO 2 gate ISFET show better sensing performance than the stack Si 3N 4/SiO 2 gate ISFET. Due to the concern of exact pH detection and high operation speed for commercial product application, the single HfO 2 gate ISFET with lower body effect on pH detection and higher transconductance is a potential candidate to integrate with an analog readout circuit.

A novel readout concept for multianode photomultiplier tubes with pad matrix anode layout

We have developed a new analog readout concept for multianode photomultiplier tubes with a pad matrix anode layout. This new readout technique is the result of a modification of a technique previously developed at the Detector Group of Jefferson Lab, (V. Popov, US patent No: 6,747,263 B1) [V. Popov, S. Majewski, A.G. Weisenberger, Readout Electronics for Multianode Photomultiplier Tubes with Pad Matrix Anode Layout, Thomas Jefferson National Accelerator Facility, IEEE 2003 Medical Imaging Conference Record, November 2003]. The new analog readout circuit provides the same analog conversion of matrix 2-D output into X and Y projective output with a significant reduction of analog outputs. The old readout network consists of resistors’ matrix and current collecting amplifiers, and it provides decoupling of each anode output into two directions (one to X and one to Y coordinates), but a decoupling function that is carried out independent of photomultiplier tube gains nonuniformity. A newly developed readout network (US patent pending) also consists of resistors’ matrix and current collecting amplifiers, but the new matrix includes an additional dumping resistor that provides an excess current from anode pad grounding. As a result, we subtract an extra current of high-gain pads in order to move the pads gain to an absolute minimum value for a given photomultiplier tube. This gain equalization procedure reduces image distortion related to gain nonuniformity. The new readout technique was used in several new radiation imaging detectors designed in the Detector Group of Jefferson Lab. It shows a visible readout uniformity and linearity improvement. The test results of an initial evaluation of this readout that is applied for data readout of four H8500 Hamamtsu PSPMT are presented.

Microsystems for multi-sensory data-acquisition

Data acquisition systems containing transducers, analog readout circuits and digital data processing capability having dimensions comparable to conventional silicon VLSI are feasible in silicon. The on-chip integration of these functions has been demonstrated and is a sound concept for the fabrication of an integrated silicon smart sensor for a single parameter. However, the complexity and data processing required in a data acquisition system for several quantities makes the concept, although technologically feasible, not economically viable. Partitioning of the various system functions over several dies and applying wafer-to-wafer bonding or using the multi-chip module is a more economically viable approach. Enhanced functionality can be obtained by using an active silicon platform as the substrate that contains all the infrastructural functions common to any instrument, such as power/thermal management, self-test and self-calibration and a local bus. In integrated chemical analysis systems, the additional advantage would be the slightly reduced packaging problem.

D-flip-flop with a programmable delay with power consumption for implementation in smart sensors

Abstract The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

Plasma ions clean and etch integrated circuits : Electronics, June 7 (1973), p.

The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

Generating pulses with C-MOS flip-flops : F. J. Marlowe and J. P. Hasili. Electronics, June (1973),p.

The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.