Analog Loop Filter Research Articles

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift

This brief presents a 10 Gb/s receiver for an application processor (AP)-to-timing controller-embedded display (TED) interface that is capable of recovering its operating frequency fast from the sleep mode under the supply voltage drift. A hybrid clock and data recovery (CDR) loop is employed to support the fast entering and exiting of the sleep mode by adding AND gates to the digital loop filter, while offering good jitter performance by utilizing an analog loop filter. Also supply voltage drift cancellation (SVDC) circuit is added to maintain constant current in the presence of supply voltage drift. Thanks to the hybrid CDR and SVDC, even if the supply voltage drift occurs during the sleep mode, the same frequency is recovered fast without frequency re-tracking. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.089mm2 with 0.99-pJ/bit energy efficiency in the active mode. The measured results show that the frequency is recovered within 36 ns even if the worst-case supply voltage drift occurs during the sleep mode.

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

Single-Event Effects Characterization of LC-VCO PLLs in a 28-nm CMOS Technology

Two-photon absorption laser experiments are conducted on a low-jitter tunable hybrid analog–digital LC -tank phase-locked loop (PLL) in a 28-nm bulk CMOS technology. The single-event effect (SEE) sensitivities for different blocks as well as the effect of varying circuit parameters are analyzed. The analog loop filter and the inductor–varactor area in the voltage-controlled oscillator (VCO) LC tank are identified as the most sensitive areas of the PLL, which generally agrees with previous studies. The VCO tail common-mode node, which was previously shown to be highly sensitive to SEE, exhibits very good robustness, thanks to the proposed second-order harmonic LC tail filter added in this design. The laser experiments show that a lower PLL bandwidth tends to reduce the SEE sensitivities of the PLL, while the results on the effect of the VCO frequency are mixed and need further study.

PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm.

A relocking scheme for optical phase locking using a digital circuit with an electrical delay line

We present a simple scheme that enables us to automatically relock optical phase locking. Our servo system consists of an analog loop filter for the fast feedback control of a high-speed controllable actuator and a digital circuit for the slow control of another actuator with a broad dynamic range. The digital circuit detects an out-of-lock status and relocks the phase locking using a signal generated by an electrical delay line. We demonstrate to relock the phase locking of a fiber-based frequency comb to a Nd:YAG laser at 1064 nm and that of an external cavity diode laser at 1156 nm to the fiber comb. The relocking scheme is attractive for various applications that employ phase locking and is especially useful for the unattended operation of optical clocks.

A Robust and Efficient Fault-Resilient Rad Hard ADPLL

Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even the traditional PLLs can’t be ported to the advanced processors. In last few years, the emergence of deep-submicron CMOS technologies have enabled digitization of major traditional analog circuits, comprising the analog PLLs that as a result could be vital to overcome above mentioned issues and to achieve more efficient solution than classical analog implementation.

Analysis and Design of VCO-Based Phase-Domain $\Sigma \Delta $ Modulators

VCO-based phase-domain $\Sigma \Delta $ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional $\Sigma \Delta $ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° ( $3\sigma $ ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m° (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.

A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications

This paper presents a voltage-controlled oscillator (VCO) based current to digital converter for sensor readout applications. Second order noise shaping of the quantization error is achieved by using implicit capacitance of the sensor to realize a passive integrator and a VCO-based quantizer. The non-linearity in voltage to frequency conversion of the VCO is tackled by placing the VCO in a loop consisting of a simple digital IIR filter and a passive integrator. The IIR filter provides large gain within the signal bandwidth and suppresses VCO input swing. As a result, non-linearity of the VCO is not exercised, thus greatly improving the proposed architecture's immunity to VCO nonlinearity. The use of a digital filter instead of an analog loop filter eases the design and makes it scaling friendly. Designed for an ambient light sensor application, the proposed circuit achieves 900 pA accuracy over an input current range of 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> A. Fabricated in a 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m CMOS process, the readout circuit consumes a total of 77.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> A current, and occupies an active area of 0.36 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^2$</tex></formula> .

Cross-layer investigation of continuous-time sigma–delta modulator under aging effects

In order to achieve reliability study in large and complex analog and mixed signal (AMS) circuits and systems, it is required to develop effective reliability-aware design methodologies and exploration tools. This paper discusses two aging mechanisms: hot carrier injection (HCI) and negative bias temperature instability (NBTI) and their effect on 65nm CMOS integrated circuits and systems (ICs). We propose an aging-aware cross-layer approach to comprehensively evaluate aging induced performance degradation at the abstraction (system) level. This approach is composed by hierarchical aging analysis at transistor/circuit level, block failure analysis at abstraction level and system-level aging considerations, which can essentially highlight sensitive blocks for circuit designers. This approach is demonstrated with a continuous-time (CT) sigma–delta (ΣΔ) modulator. Analog loop filter and clock distributor are studied with failure boundary and transistor level aging simulation. The aging investigation approach reports system level aging-aware consideration of these building blocks. Results show that amplifiers in analog loop filter have enough margin to cope with aging induced degradations. However, aging risk exists in clock circuits, especially when implementing with high Vt transistors. NBTI induced clock jitter from clock distributor can influence clocked block in CT ΣΔ modulator and degrade signal-to-noise ratio (SNR).

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration

This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancellation of the ΔΣ quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is -105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.

Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems

Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indicating that the system is prone to be unstable. Stability analysis of the BPLLs is conducted to derive stability conditions, taking advantage of the radius of curvature technique to facilitate numerical calculations involved. It is shown that the stability conditions depend on the LF parameters, the loop delay, and the update time of the BPLLs.

A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control

A 1.1 GHz semi-digital fractional-N PLL without the time-to-digital converter (TDC) whose resolution and linearity heavily depends on process and temperature variations is implemented in 65 nm CMOS. A hybrid loop control with a fully differential proportional-gain path and embedded finite-impulse response (FIR) filtering achieves linear phase tracking as well as good technology scalability, having a small analog loop filter area less than 0.01 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> . The use of the hybrid FIR filter not only suppresses out-of-band quantization noise of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Delta\Sigma$</tex> </formula> modulator but also improves the linearity of the proportional-gain path. The TDC-less semi-digital PLL consumes 1.75 mW from a 0.9 V supply voltage, achieving significant power reduction compared to conventional all-digital PLLs.

Hardware-Accelerated Simulation Environment for CT Sigma&amp;#x2013;Delta Modulators Using an FPGA

In this brief, a hardware-accelerated simulation environment for continuous-time (CT) $\Sigma\Delta$ modulators is presented. Due to the presence of the nonlinear quantizer, simulating $\Sigma\Delta$ modulators is a complicated task in general. The simulation of CT modulators is even more time consuming than that of their discrete-time counterparts, due to the analog loop filter. In particular, in an automated design environment, a large number of simulations have to be performed during the design process of $ \Sigma\Delta$ modulators. In this brief, it is shown for the first time that the system-level emulation of CT $\Sigma\Delta$ modulators on an field-programmable gate array results in a significant acceleration, reducing the simulation time by a factor of more than $\hbox{10}^{5}$ compared to a commonly used Simulink simulation. This allows simulating 10 000 of modulators per second, enabling the use of heuristic search algorithms for real-time design for CT $\Sigma\Delta$ modulators.

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators

In cascaded ΔΣ modulators (DSMs), the quantization noise of the earlier stage leaks to the output unless completely cancelled by the digital noise cancellation filter (NCF). The noise leakage is worse in the continuous-time (CT) implementation due to the poorly controlled time constant of the analog loop filter. A parameter-based continuous-time to discrete-time transform is developed to get an exact digital NCF, and the analog filter time constant is calibrated to match with the digital NCF. A binary pulse tone is injected into the quantizer to detect the filter time-constant error, and eliminated by zero-forcing its residual power based on the adaptive least-mean-square (LMS) algorithm. A 2-1-1 cascaded CT-DSM prototype in 0.18-μm CMOS demonstrates that the spectral density of the leaked noise is lower than 10 nV/?Hz after the capacitors in the Gm-C loop filters are trimmed with 1.1% step. With a 1-Vpp full-scale input, it achieves a dynamic range of 68 dB within 18-MHz bandwidth at an over-sampling ratio of 10. The analog core and the digital logic occupy 1.27 mm2,and consume 230 mW at 1.8 V.

Design Considerations for Cascade $\Delta \Sigma $ ADC's

This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter.

A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 µm CMOS process occupies 0.35 mm2 active area. From a 1.8 V supply, it consumes 59 mW and 984 µW during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems

A fast f c automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled G m -C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of f c tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast f c automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200μs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average f c of 2.12 MHz.

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a lot of communications systems, in particular in the area of clock and data recovery. Although most of the BBPLLs implemented up to now use analog loop filters, the binary output of the phase detector naturally lends itself to a digital implementation. In this paper, the nonlinear dynamics of first- and second-order digital BBPLLs is analyzed from a design perspective. In particular, the effects of loop delays on the PLL performances are emphasized. Conditions for the existence of orbits (limit cycles) are derived, and the timing jitter performances are evaluated. Finally, useful expressions for the design and optimization of the PLL parameters for low jitter are given.