Analog Layout Research Articles

SWA: SoftWare for Analog Design Automation

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min.

BAG2-assisted analog layout synthesis for TSMC 65 nm and GPDK 45 nm

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continuing to be developed and targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley Analog Generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow and it encourages design reuse due to using parameterized generators which can be scaled as required. This reduces the layout development time compared to manual handmade layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65 nm and Cadence GPDK 45 nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

Placement is a critical step in layout automation for analog and mixed-signal (AMS) integrated circuits (IC). It determines the proximity of devices and influences the wiring topology, significantly impacting post-routing parasitics and coupling capacitance. Existing analog placement techniques mainly focus on geometric constraints in analog building blocks. However, there yet lacks an effective way to consider the system-level signal flow for sensitive AMS circuits. Leveraging prior knowledge from schematics, we propose considering the critical signal paths in automatic AMS placement. A multilevel analog layout automation flow is further developed to reduce manual efforts in synthesizing hierarchical AMS circuits. Experimental results demonstrate the efficiency and effectiveness of our proposed framework with a 22.8% reduction in routed wirelength compared to state-of-theart AMS placer and a 10 dB improvement in the signal-to-noiseand-distortion ratio (SNDR) for an ADC.

Interactive Analog Layout Editing With Instant Placement and Routing Legalization

Analog layout design is still primarily reliant on manual efforts. Current fully automated workflows are unable to meet the expectations for flexible customization and are incompatible with existing manual workflows. For both performance and productivity, interactive layout editing has the ability to bridge the gap between manual and automated flows. We present an interactive layout editing system in this study that includes well-defined commands for both placement and routing customization. This is a pioneering work that provides a holistic study on the interactive design methodology for analog layouts and its capability of speeding up design closure. Our framework comes up with the instant placement legalization and routing adjustment mechanism for rapid layout update and modification. The framework is capable of handling real-time user interaction and improving the performance of fully automated layout generators verified by post-layout simulation on real-world analog designs. Experimental results demonstrate the performance enhancement on real-world analog designs with only a few editing commands. As examples, on the low-dropout regulator, our framework can reduce the overshot down and up voltage to nearly <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/3$ </tex-math></inline-formula> of layout generated by automation tool with two editing commands, and on the operational transconductance amplifier, it achieves 33.5% better common mode rejection ratio with only one command.

Generating the Generator: A User-Driven and Template-Based Approach towards Analog Layout Automation

Various analog design automation attempts have addressed the shortcomings of the still largely manual and, thus, inefficient and risky analog design approach. These methods can roughly be divided into synthesis and procedural generation. An important key aspect has, however, rarely been considered: usability. While synthesis requires sophisticated constraints, procedural generators require expert programmers. Both prevent users from adopting the respective method. Thus, we propose a new approach to automatically create procedural generators in a user-driven way. First, analog generators, which also create symbols and layouts, are utilized during schematic entry to encapsulate common analog building blocks. Second, automatic code creation builds a hierarchical generator for all views with the schematic as input. Third, the approach links the building block generators with the layout through an object-oriented template library that is accessible through generator parameters, allowing the user to control the arrangement. No programming is required to reach this state. We believe that our approach will significantly ease the transition of analog designers to procedural generation. At the same time, the templates allow for a “bridge” to open frameworks and synthesis approaches so that the methodologies can be both better spread and combined. This way, comprehensive frameworks of both synthesis-based and procedural-based analog automation methods can be built in a user-driven way, and designers are enabled to gain early layout insight and ease IP reusability.

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

MAGICAL is an open-source system for analog and mixed-signal (AMS) circuit layout synthesis. Using custom place-and-route and constraint extraction algorithms, MAGICAL provides a fully-automated layout implementation flow. MAGICAL 1.0 has been proven in silicon with a 40-nm 1GS/s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC. The source code has been released to enable broad usage. Recently, MAGICAL has also been extended to cover more circuit classes such as SAR-ADC. This tutorial/perspective paper describes the overall MAGICAL framework and algorithms. We also provide a tutorial on how to use and extend MAGICAL and discuss future research directions for AMS layout design automation.

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings

This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

This paper presents an analog layout generator based DLDO with a self-triggered binary search windowed flash ADC in 22nm CMOS. A self-triggered binary search mechanism with a delay-based architecture is proposed to reduce the exponentially growing kickback noise and energy consumption of a traditional flash ADC down to the level of a SAR ADC while maintaining its high-speed feature. To conquer the complexity bottleneck of SoC development in FinFET technology, a practical analog layout generation framework is proposed to maximize the productivity of implementing analog circuit blocks in scaled CMOS process. To meet the performance, area and reliability specifications across a variety of circuits, the methodology allows varying levels of constraints from designers, thus significantly improving the physical design time & effort up to 60× compared with conventional manual approach. The DLDO features 3.55ps FoM and fully automatic generation.

Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models

The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder-decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder-decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder-only, decoder-only, and encoder-decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools

Today’s analog and mixed-signal (AMS) layout flow requires long manual iterations and does not leverage computing resources for data-driven optimization. This issue is further compounded by the explosion of design rules and layout-dependent effects (LDEs). We present an AMS layout generation flow that leverages digital place-and-route (PnR) tools, amortizes setup cost with reusable primitives, and prunes layout candidates using a fast evaluation scheme. We also analyze LDEs and parasitics and investigate unique challenges and mitigation strategies associated with using digital PnR tools for AMS circuits. These insights are validated with a generated StrongARM comparator and a voltage-controlled oscillator (VCO). The VCO layout was optimized in 2 h and fabricated in 16-nm FinFET CMOS. Silicon measurement results of the VCO closely track the simulation, verifying the methodology from netlist to silicon.

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically. In the proposed method, layout effects are considered during the layout generation. Layout parasitics and geometry information are extracted from a new automated layout generator. In this method, the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as an optimization algorithm. In order to verify the performance of the proposed method, the design of three-stage operational amplifier (op-amp) and two-stage class-AB operational trans-conductance amplifier (OTA) in a 0.18µm process CMOS technology with 1.8 V supply voltage are presented. The simulation results indicate the efficiency of the proposed analog layout generation method.

Temporal Computing With Superconductors

Creating computing systems able to address our ever-increasing needs, especially as we reach the end of CMOS transistor scaling, will require truly novel methods of computing. However, the traditional logic abstractions and the digital design patterns we understand so well have coevolved with the hardware technology that has embodied them. As we look past CMOS, there is no reason to think that those same abstractions best serve to encapsulate the computational potential inherent to emerging devices. We posit that a new and radically more efficient foundation for computing lies at the intersection of superconductor electronics and delay-coded computation. Building on recent work in race logic, we show that superconducting circuits can naturally compute directly over temporal relationships between pulse arrivals; that the computational relationships between those pulse arrivals can be formalized through a functional extension to a temporal predicate logic used in the verification community; and that the resulting architectures can operate asynchronously and describe real and useful computations. We verify our hypothesis through a combination of detailed analog circuit models and layout designs, a formal analysis of our abstractions, and an evaluation of several superconducting temporal accelerators.

Challenges and opportunities toward fully automated analog layout design

Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

Wire Load Oriented Analog Routing with Matching Constraints

As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.

LDE-aware Analog Layout Migration with OPC-inclusive Routing

Performance degradation in analog circuits due to layout dependent effects (LDEs) has become increasingly challenging in advanced technologies. To address this issue, LDEs have to be seriously considered as performance constraints in the physical design process. In this article, we have proposed an innovative LDE-aware retargeting methodology for analog layout migration from old technologies to new ones with LDEs optimized for performance preservation. The LDE constraints, which are first identified with the aid of a specialized sensitivity analysis scheme, are satisfied during the layout migration process. Moreover, optical proximity correction (OPC), as one of the most popular resolution enhancement techniques for subwavelength lithography in modern nanometer technology manufacturing, is also included in this study. We have developed an OPC-inclusive ILP-based analog router to route electrical nets for improving image fidelity of the final layout while the routability and other analog constraints are respected in the meantime. The experimental results show our proposed layout migration methodology along with the routing scheme is able to retarget analog layouts with better circuit performance and finer image quality compared to the previous works.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with a limited DCO tuning range of only 7.3–8.7 GHz (±8.7%). Phase modulation of narrowband signals (e.g., one resource block) using DTC could result in spurs in output spectrum due to the almost periodic nature of DTC errors. A theoretical analysis is presented that predicts the location of these spurs and a technique to eliminate such spurs by appropriately adjusting the PLL frequency is introduced. A new digitally controlled-edge-interpolator architecture is also presented to minimize dynamic errors, which is necessary in order to meet stringent cellular noise requirements. The DTC was implemented using digital synthesis and auto-place-and-route (APR) tools, requiring very limited analog layout resources. The TX was fabricated in 14-nm FinFET and it achieved a noise of −153/−150 dBc/Hz for LTE5/LTE20 in Band1 at +4-dBm output power with DTC power dissipation of 27 mW.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153 dBc/Hz Noise in 14-nm FinFET

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) to enable high-efficiency polar RFDAC for multiband and wide-channel applications. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with DCO tuning range of only 7.3-8.7 GHz (±8.7%). The TX was fabricated in 14-nm FinFET and achieves noise of -153/-150 dBc/Hz for LTE5/LTE20 in Band1 with DTC power dissipation of 27 mW. The DTC was implemented using digital Automatic-Place-and-Route tools, requiring very limited analog layout resources.

ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress

The IARPA SuperTools program requires the development of superconducting electronic design automation (S-EDA) and superconducting technology computer-aided design (S-TCAD) tools aimed at enabling the reliable design of complex superconducting digital circuits with millions of Josephson junctions. Within the SuperTools program, the ColdFlux project addresses S-EDA and S-TCAD tool research and development in four areas: 1) RTL synthesis, architectures and verification; 2) analog design and layout synthesis; 3) physical design and test; and 4) device and process modeling/simulation and cell library design. Capabilities include, but are not limited to, the following: device level modeling and simulation of Josephson junctions, modeling and simulation of the superconducting process manufacturing processes, powerful new electrical circuit simulation, parameterized schematic and layout libraries, optimization, compact SPICE-like model extraction, timing analysis, behavioral, register-transfer-level and logic syntheses, clock tree synthesis, placement and routing, layout-versus-schematic extraction, functional verification, and the evaluation of designs in the presence of magnetic fields and trapped flux. ColdFlux consists of six research groups from four continents. Here, we present an overview of the current and planned activities related to the project and justify the design assumptions and decisions that were made to allow the development of design tools for million-gate circuits.

High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction

As the technology node continuously scales down, layout-dependent effects (LDEs) have been significantly affecting the threshold voltage and mobility of MOSFET transistors and then, in turn, the performance of analog integrated circuits. In this paper, we propose an LDE optimization methodology based on the evolutionary algorithm, which aims to protect analog circuits from the LDE-induced circuit performance degradation. With the aid of a fast analog layout retargeting scheme, our proposed optimization can evaluate the circuit performance with the consideration of detailed physical layouts, tune the device placement and transistor finger number, and modify the layout patterns for the LDE-aware circuit performance preservation. To accelerate the physical layout synthesis, our new retargeting process supports general device abstraction. The experimental results show that our proposed methodology can more effectively preserve analog and even RF circuit performance with higher efficiency than the alternative approaches.