Analog Integrated Circuits Research Articles

Novel GA‐OCEAN Framework for Automatically Designing the Charge‐Pump Circuit

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

The complex analog and mixed-signal transceivers where overall system performance is often limited by the weakest performing subsystem. While analog and mixed-signal integrated circuits have significantly advanced, the future of 5G and 6G transceiver design could be accelerated by including artificial intelligence. In this combination, analog integrated circuit design and operation would harness machine learning to identify, characterize, and act upon variations and anomalies in system performance. Focusing on 5G and 6G, this paper investigates solutions for a unified intelligent integrated transceiver: a conceptual combination of a traditional analog subsystem, a supporting digital subsystem that enables artificial intelligence, and dedicated feedback circuitry or sensors that monitor performance, efficiency, or reliability. Active and passive components and propagation channels are reviewed based on their merits of introducing intelligence. Holistically and for broader applicability, the paper conceptualizes and coins the notion of an ‘‘intelligent integrated system (IIS)’’, which brings forward a novel unified vision and approach toward context-aware subsystems that dynamically interact with ambient and varying operating conditions. To demonstrate viability, the paper concatenates a select set of measurement results.

Phase sensitive detection for embedded sensors

The measurement of some physical properties requires detection of both amplitude and phase of an applied test signal. In portable sensors, this needs to be performed locally with integrated analog circuits or digital processing. Wireless sensor network allows the measurements over wide areas but raises a challenge of using efficient algorithm for phase sensitive detection (PSD) in nodes with constrained processing capacity. It is not straightforward to compare different PSD methods because their performance is closely related to the fine tuning of their parameters such as filter order and cut-off frequency. We propose a methodology to compare several PSD methods subjected to the same response time to assess its ability to provide accurate estimation in the presence of noise. We also determine the computational complexity of the investigated methods in terms of the number of operations required. We investigate both continuous and windowed operation. The methods were tested through simulations and verified using a dedicated embedded system. Our findings demonstrate that Goertzel algorithm rendered the best results, with smaller estimation error and less computation complexity.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

A Comprehensive Study of Different Techniques for Voltage References

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

In this work, an analytical model for a twin gate Tunnel Field Effect Transistor's drain current operating in the subthreshold and superthreshold regions is proposed. Using this drain current model, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved. Due to the simplicity of this approach, it may be quickly implemented for any type of dual gate TFETs by adjusting a few parameters. Comparing the drain current calculated by this analytical model to the drain current simulated by the 2D-Sentaurus TCAD software demonstrates the Tunnel FET's authenticity. The proposed analytical method can be used to achieve the appropriate transconductance for operating Tunnel FETs in the gigahertz region with very low milliwatt power consumption.

Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning

This article presents a novel deep-reinforcement-learning-based method for topology synthesis of analog-integrated circuits, especially operational amplifiers (OpAmps). It behaves like a human designer, who learns from trials, derives design knowledge and experience, and evolves gradually to finally figure out optimal manners to construct proper circuit topologies that meet design specifications. Essential design rules are defined and applied to set up the specialized environment for reinforcement learning in order to reasonably construct circuit topologies with building blocks as the basic components. Our proposed method can not only handle large-size circuit designs but also generate creative circuit topologies. The produced circuit topologies are verified by the simulation-in-loop sizing. In order to improve the evaluation efficiency, hash table and symbolic analysis techniques are utilized to significantly reduce the number of the produced topologies to be sized during the synthesis process. Compared with the state-of-the-art approaches, our proposed method significantly improves the synthesis efficiency by consuming only several hours on average to produce a trustworthy solution. Our experimental results demonstrate its sound efficiency, strong reliability, and wide applicability.

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

Towards Low-Power Machine Learning Architectures Inspired by Brain Neuromodulatory Signalling

We present a transfer learning method inspired by modulatory neurotransmitter mechanisms in biological brains and explore applications for neuromorphic hardware. In this method, the pre-trained weights of an artificial neural network are held constant and a new, similar task is learned by manipulating the firing sensitivity of each neuron via a supplemental bias input. We refer to this as neuromodulatory tuning (NT). We demonstrate empirically that neuromodulatory tuning produces results comparable with traditional fine-tuning (TFT) methods in the domain of image recognition in both feed-forward deep learning and spiking neural network architectures. In our tests, NT reduced the number of parameters to be trained by four orders of magnitude as compared with traditional fine-tuning methods. We further demonstrate that neuromodulatory tuning can be implemented in analog hardware as a current source with a variable supply voltage. Our analog neuron design implements the leaky integrate-and-fire model with three bi-directional binary-scaled current sources comprising the synapse. Signals approximating modulatory neurotransmitter mechanisms are applied via adjustable power domains associated with each synapse. We validate the feasibility of the circuit design using high-fidelity simulation tools and propose an efficient implementation of neuromodulatory tuning using integrated analog circuits that consume significantly less power than digital hardware (GPU/CPU).

Specific Design Features of Charge Sensitive Amplifiers on Arsenide-Gallium Master Slice

For the production of integrated analog circuits with a small-scale integration, which are developed to operate at temperatures up to minus 200 ℃ and/or with absorbed dose of gamma radiation up to 5 Mrad, a gallium arsenide master slice has been created. The following types of active elements are used in this master slice: DpHEMT with gate dimensions 100 ηm/0,2 ηm and 10 ηm/0,2 ηm; p-n-p HBT, they were chosen for realization of most common analog circuits of operational amplifiers, comparators, voltage followers. Despite the small number of available DpHEMT with high transconductance for circuit synthesis and volt-ampere characteristics features of DpHEMT experimental samples, which exclude use of those transistors at low drain current, master slice give opportunity for developing charge-sensitive amplifiers (CSA) circuits with only one type of active elements – DpHEMT. At the same time, correct choice of the operating point of transistors provide development of low-noise, high-speed CSAs with better parameters than silicon CSAs for sensors with internal capacitance up to 100 pF. So, developed on GaAs master slice CSA with head DpHEMTs and ratio of the gate width to its length, equal to W/L = 2000 and W/L = 3000, characterized by current consumption ICC = 5,46 mA and ICC = 5,25 mA, rise time tR = 10,7 ns and tR = 9,6 ns, equivalent noise charge ENC = 3960 el, and ENC = 3700 el. with sensor capacitance of 50 pF, while the CSA with a head silicon p-channel junction field-effect transistor has W/L = 3870, ICC = 6,99 mA, tR = 27,7 ns, ENC = 5360 el. with the same sensor capacitance.

RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques.

For electronic products, printed circuit boards are employed to fix integrated circuits (ICs) and connect all ICs and electronic components. This allows for the smooth transmission of electronic signals among electronic components. Machine learning (ML) techniques are popular and employed in various fields. To capture the nonlinear data patterns and input–output electrical relationships of analog circuits, this study aims to employ ML techniques to improve operations from modeling to testing in the analog IC packaging and testing industry. The simulation calculation of the resistance, inductance, and capacitance of the pin count corresponding to the target electrical specification is a complex process. Tasks include converting a two-dimensional circuit into a three-dimensional one in simulation and modeling-buried structure operations. In this study, circuit datasets are employed for training the ML model to predict resistance (R), inductance (L), and capacitance (C). The least squares support vector regression (LSSVR) with Genetic Algorithms (GA) (LSSVR-GA) serves as an ML model for forecasting RLC values. Genetic algorithms are used to select parameters of LSSVR models. To demonstrate the performance of LSSVR models in forecasting RLC values, three other ML models with genetic algorithms, including backpropagation neural networks (BPNN-GA), random forest (RF-GA), and eXtreme gradient boosting (XGBoost-GA), were employed to cope with the same data. Numerical results illustrated that the LSSVR-GA outperformed the three other forecasting models by around 14.84% averagely in terms of mean absolute percentage error (MAPE), weighted absolute percent error measure (WAPE), and normalized mean absolute error (NMAE). This study collected data from an IC packaging and testing firm in Taiwan. The innovation and advantage of the proposed method is using a machine approach to forecast RLC values instead of through simulation ways, which generates accurate results. Numerical results revealed that the developed ML model is effective and efficient in RLC circuit forecasting for the analog IC packaging and testing industry.

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation

With continued scaling, the transistor aging induced by hot carrier injection (HCI) and bias temperature instability (BTI) causes an increasing failure of nanometer-scale integrated circuits (ICs). Compared to digital ICs, analog ICs are more susceptible to aging effects. The industrial large-scale analog ICs bring grand challenges in the efficiency of aging verification. In this article, we propose a heterogeneous graph convolutional network (H-GCN) to fast estimate aging-induced transistor degradation in analog ICs. To characterize the multityped devices and connection pins, a heterogeneous directed multigraph is adopted to efficiently represent the topology of analog ICs. A latent space mapping method is used to transform the feature vector of all typed devices into a unified latent space. We further extend the proposed H-GCN to be a deep version via initial residual connections and identity mappings. The extended deep H-GCN can extract information from multihop devices without an oversmoothing issue. A probability-based neighborhood sampling method on the bipartite graph is adopted to ease the model training on large-scale graphs and achieve good scalability. Experiments on very advanced 5-nm industrial benchmarks show that, compared to traditional graph learning methods and static aging reliability simulations by an industrial design-for-reliability (DFR) tool, the proposed deep H-GCN can achieve more accurate estimations of aging-induced transistor degradation. Compared to the dynamic and static aging reliability simulations, our extended deep H-GCN, on average, can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$241\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$39\times $ </tex-math></inline-formula> speedup, respectively.

Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models

The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder-decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder-decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder-only, decoder-only, and encoder-decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

Guest Editors' Words

The demand for analog and mixed-signal integrated circuits has increased significantly in the last decades, although we have been living in a “digital era”. One of the reasons for such high demand is simply explicated by the increase of devices in our daily life. Such scenario can be simply called as “Ubiquitous computing” and/or the Internet of Everything. This Special Issue brings ten invited papers from experts in the field. The readers will be provided with an extensive literature review.

Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security

We propose an antipiracy security approach for programmable analog and mixed-signal (AMS) integrated circuits (ICs). The security approach relies on functionality locking by leveraging the inherent programmability and utilizing the configuration settings as secret keys or, equivalently, the programming bits as key bits. When invalid keys are applied, the circuit is untuned and, as a result, its functionality breaks, i.e., at least one of the performances violates its specification. As long as the calibration algorithm that produces the configuration settings can be kept secret, the proposed approach can serve as a countermeasure against all types of counterfeiting, i.e., cloning, overbuilding, remarking, and recycling. An important advantage of the proposed approach is that it is lock-less. It leaves the design intact, there is no change to the design flow, and there are no performance penalty and no area or power overheads due to the lock operation. We demonstrate it on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula> analog-to-digital converter (ADC) with 194-bit programmability and complex calibration algorithm used in the context of highly digitized, multistandard RF receivers.

The Hidden Potential of Polysilsesquioxane for High‐k: Analysis of the Origin of its Dielectric Nature and Practical Low‐Voltage‐Operating Applications beyond the Unit Device

AbstractLow‐voltage‐operating high‐performance organic field‐effect transistors (OFETs) are regarded as the building blocks of analog and digital integrated circuits for next‐generation electronics. To fulfill this, such an OFET must have high‐dielectric constant (k) characteristics for increasing the capacitance values to make enough of a field‐effect charge, a hydrophobic surface that does not cause charge trapping, and a low leakage current property to guarantee operating stability. This study demonstrates a new strategy to induce high‐k characteristics (&gt;8) with durable polysilsesquioxane (PSQ)‐based dielectrics. This strategy involves realizing a dipolar side‐chain reorientation under an electric field and its applications to low‐voltage‐driving OFETs showing high field‐effect mobility levels as high as 27 cm2 V–1 s–1. Different PSQs are characterized, and the differences in their characteristics lead to distinct polarization phenomena, resulting in different hysteresis behaviors during device operation. The printed unit devices can also be fabricated on flexible platforms and integrated devices through these materials and show robust switching or memory performances under low‐voltage‐operation conditions. Therefore, this facile but powerful synthesis strategy for high‐k PSQ dielectrics can pave a new path for the production of practical printable high‐k dielectrics for organic electronics and hence realize next‐generation integrated electronics.

Margarethenhöhe goes towards low-carbon area - sustainable concepts for energy-efficient built heritage

Within the framework of a project funded by the Federal Ministry of Economics and Energy (BMWi) in Germany, it is being examined how, with different approaches, even historic buildings can contribute to an energy-efficient heritage district. Five partners are investigating the legal, structural and technical conditions for improving the building envelope in line with the preservation order, modernizing the buildings and providing a future-oriented energy supply. The inclusion of renewable energies and the digital networking of all components is of particular importance. For this all suitable measures will be adapted in five buildings for demonstration. Then, on basis of an extensive monitoring, the theoretically elaborated model approaches and the results obtained by means of numerical simulations can be validated. The joint project started in 2016. The IWB of University of Stuttgart as coordinator, the Margarethe Krupp Foundation as owner, the Gas and Heat Institute Essen e.V. and two institutes of the RWTH Aachen University, the Institute for Integrated Analog Circuits and the Institute for Building and Climate Technology, are partners in the research network.

Reduction of total harmonic distortion of three-phase inverter using alternate switching strategy

Alternating current (AC) electrical drives mainly require smaller current (or torque) ripples and lower total harmonic distortion (THD) of voltage for excellent drive performances. Normally, in practice, to achieve these requirements, the inverter needs to be operated at high switching frequency. By operating at high switching frequency, the size of filter can be reduced. However, the inverter which oftenly employs insulated gate bipolar transistor (IGBT) for high power applications cannot be operated at high switching frequency. This is because, the IGBT switching frequency cannot be operated above 50 kHz due to its thermal restrictions. This paper proposes an alternate switching strategy to enable the use of IGBT for operating the inverter at high switching frequency to improve THD performances. In this strategy, each IGBT in a group of switches in the modified inverter circuit will operate the switching frequency at one-fourth of the inverter switching frequency. The alternate switching is implemented using simple analog and digital integrated circuits.

A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

An analytic method for parameter extraction of InP HBTs small-signal model

PurposeHigh-speed Indium Phosphide (InP) HBTs have been widely used to design high-speed analog, digital and mixed-signal integrated circuits. The purpose of this study is to propose a new parameter extraction procedure for determining an improved T-topology small-signal equivalent circuit of InP heterojunction bipolar transistors (HBTs).Design/methodology/approachThe alternating current crowding effect is considered through adding the intrinsic base capacitance in the small-signal equivalent circuit. All of the circuit parameters are extracted directly without using any approximation.FindingsThe extraction technique is more easily understood and clearer than other extraction methods, as the equations are derived from the S-parameters by peeling peripheral elements from small-signal models to get reduced ones and extracting each equivalent-circuit parameter using each equation.Originality/valueTo validate the presented parameter extraction technology, an n-p-n emitter-up InP HBT was analyzed adopting the method. Excellent agreement between measured and modeled S-parameters is obtained up to 40 GHz.