Analog Integrated Circuit Design Research Articles

Novel GA‐OCEAN Framework for Automatically Designing the Charge‐Pump Circuit

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Analog and Mixed-signal Integrated Circuits of 5Gand 6G Data Communication

The complex analog and mixed-signal transceivers where overall system performance is often limited by the weakest performing subsystem. While analog and mixed-signal integrated circuits have significantly advanced, the future of 5G and 6G transceiver design could be accelerated by including artificial intelligence. In this combination, analog integrated circuit design and operation would harness machine learning to identify, characterize, and act upon variations and anomalies in system performance. Focusing on 5G and 6G, this paper investigates solutions for a unified intelligent integrated transceiver: a conceptual combination of a traditional analog subsystem, a supporting digital subsystem that enables artificial intelligence, and dedicated feedback circuitry or sensors that monitor performance, efficiency, or reliability. Active and passive components and propagation channels are reviewed based on their merits of introducing intelligence. Holistically and for broader applicability, the paper conceptualizes and coins the notion of an ‘‘intelligent integrated system (IIS)’’, which brings forward a novel unified vision and approach toward context-aware subsystems that dynamically interact with ambient and varying operating conditions. To demonstrate viability, the paper concatenates a select set of measurement results.

Evolutionary Optimization Techniques in Analog Integrated Circuit Designs

The proposed genetic algorithm (GA) and particle swarm optimization (PSO) applied for the optimal design of a one-stage operational amplifier circuit with a current mirror load are studied in this work. The sizes of transistors are optimized using the proposed GA and PSO for improved areas and performance parameters of the circuit. A number of performance parameters are collected from the data set created by GA and PSO to optimize the size of transistors and other design parameters. The Spectre simulator is chosen for the simulation of circuit parameters to obtain necessary for the GA and PSO algorithm. Post-optimization results justify that the proposed GA and PSO methods are competitive with differential evolution regarding convergence speed, design specifications, and the optimal CMOS one-stage operational amplifier circuit parameters.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Systematic Design of a Pseudodifferential VCO Using Monomial Fitting

Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles. This paper proposes a new systematic design approach for the sizing of analogue integrated circuits to address this issue. The method utilises a surrogate optimisation technique that approximates a simple monomial function based on few simulation results. These monomials are convex and can be optimised using a simple linear optimisation routine, resulting in a single global optimal solution. We show that monomial functions, in many cases, have an analytic relation to integrated circuits, making them well suited for the application. The method is demonstrated by designing a 14 MHz pseudodifferential voltage-controlled oscillator (VCO) with minimised current consumption and is manufactured in a 180 nm process. The measured total current matches the predicted and is lower than that for other similar state-of-the-art VCOs.

Performance evaluation of evolutionary algorithms for analog integrated circuit design optimisation

An automated sizing approach for analog circuits using evolutionary algorithms is presented in this paper. A targeted search of the search space has been implemented using a particle generation function and a repair-bounds function that has resulted in faster convergence to the optimal solution. The algorithms are tuned and modified to converge to a better optimal solution with less standard deviation for multiple runs compared to standard versions. Modified versions of the artificial bee colony optimisation algorithm, genetic algorithm, grey wolf optimisation algorithm, and particle swarm optimisation algorithm are tested and compared for the optimal sizing of two operational amplifier topologies. An extensive performance evaluation of all the modified algorithms showed that the modifications have resulted in consistent performance with improved convergence for all the algorithms. The implementation of parallel computation in the algorithms has reduced run time. Among the considered algorithms, the modified artificial bee colony optimisation algorithm gave the most optimal solution with consistent results across multiple runs.

Deep Neural Networks-Based Direct-Current Operation Prediction and Circuit Migration Design

Recently, design methods based on gm/Id parameters have attracted attention in analog integrated circuit design and have been automated with computer assistance. However, the look-up tables (LUTs) in the gm/Id method have the problem of high hardware resource overhead. To address this issue, this paper proposes a multi-output deep neural network (DNN) structure for modeling the direct-current parameters of transistors and replacing LUTs for circuit design. The proposed DNN models’ performance is verified using mainstream design technologies such as TSMC 40 nm (T40), TSMC 65 nm (T65), TSMC 180 nm (T180), and SMIC 180 nm (S180). Compared with LUTs, the proposed DNN models are able to reduce at least 99.9% storage space occupation and 95.62% prediction time overhead with a mean absolute percentage error of less than 0.2%. In addition, we propose an automated circuit migration design method using DNN models in different technologies, combined with gm/Id parameters. The method generates circuit design databases in different technologies and obtains device design results according to performance requirements. The experimental results show that using DNN models can reduce the time overhead by more than 40% compared to using LUTs. The simulation results of circuit transplantation design show that the circuit performance of T40, T65, S180, and T180 meets the requirements, which verifies the proposed DNN-based automated circuit design method.

Analog integrated circuit design with machine learning

Due to the widespread application of semiconductor technology in integrated circuits, more and more design studies on analog integrated circuits are gradually being implemented. However, due to the nature of analog integrated circuits, it is time-consuming and inefficient. Therefore, there are lots of experts studying how to reduce the design cycle of analog ICs. The use of machine learning in analog circuits stands out, as machine learning-based design methods have significantly reduced the analog cycle time. This review report will first introduce the algorithms related to machine learning, and the second half will outline the existing applications of machine learning in an analog integrated circuit and compare them.

The Research of Integrated Circuit Design Technology

This article discusses the fundamentals of analogue integrated circuit design and construction, as well as the operation and some basic models of MOS transistors. It also provides a thorough introduction to the CMOS, PMOS, and NMOS structures, as well as the benefits and drawbacks of each. Additionally, operational and differential amplifiers are introduced, along with some examples of their uses. While attending summer school, I also learned how to simulate the SPEICE model using the computer program CoolSPICE. The SPEICE model is a literal description of a circuit component that theoretically predicts the behavior of that component under various conditions. The article ends with forecasts and suggestions regarding the future evolution of analog circuits and their potential effects on society.

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog integrated circuit design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: 1) the prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent and 2) the machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called efficient surrogate model-assisted sizing method for high-performance analog building blocks (ESSAB), is proposed in this article to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performance. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation

Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-the-art machine learning techniques used in analog circuit sizing and analyze their effectiveness in achieving the desired goals; (2) to point out the remaining open challenges, as well as the most relevant research directions to be explored. Finally, the different analog circuits on which machine learning techniques were applied are also presented and their results discussed from a circuit designer perspective.

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.

Slice-Based Analog Design

Advances over the last decades in electronic design automation (EDA) for the design of digital integrated circuits (ICs), have led to the development of a robust set of tools and methodologies that automate almost all low-level phases of the digital design workflow. In contrast, analog IC design remains a mostly handmade, time-consuming and knowledge-intensive process. The amount of design iterations can be heavily cut down by the use of realistic value tables through the $g_{m}/I_{D}$ design technique; however, the process still remains time-consuming and error-prone, with an end result of limited applicability beyond the scope of the initial specifications. The slice-based design methodology, first introduced in this paper, is a new approach to analog IC design, suitable for implementation in EDA tools, that aims to reduce the amount of time and expertise required from the user. This methodology, inspired by the $g_{m}/I_{D}$ design technique, is based on the use of pre-designed circuit cells, which can be connected in parallel to scale important performance metrics. Although not limited to any particular fabrication process, the present paper explores the application of the proposed design methodology to CMOS technologies, and in the context of a particular target application: low-noise charge-sensitive amplifiers (CSA) used for instrumentation in particle physics experiments. The methodology was successfully applied and validated through the design, fabrication and testing of a CSA with configurable noise performance.

Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing

The design of analog and mixed-signal integrated circuits (ICs) is intricate due to the continuous nature of the signals handled. Still, it is also strongly affected by the physical implementation of analog devices on the circuits’ layout. The circuit layout corresponds to the physical implementation of an analog IC used in fabrication that describes its devices geometrically. As circuits’ integration and device sizes shrink, the physics of the interactions between devices, as they are placed in the layout, was proved to easily drive analog and mixed-signal ICs from promising pre-layout performances to completely post-layout malfunction. As these layout-dependent effects (LDEs) can only be evaluated once the layout is completed, the true post-layout performance is only evaluated in a late stage of the traditional design flow, causing expensive redesign iterations lacking the information that identifies precisely where, in the layout, there are problems needed to be solved. For technologies above the 40-nanometers, the leading causes of LDEs are mobility and threshold voltage variations. This paper proposes an automatic device placement methodology that explicitly accounts for, and minimizes, these LDEs. An absolute representation of the floorplan is adopted, and, multiple optimization techniques, including the novel, constrained archive-based multi-objective implementation of the simulated quantum annealing inspired algorithm, enhanced with specific LDE-impact mitigation operators are applied to solve the problem. In each of these optimization processes, established LDE formulations for accurate circuit simulation models are used to evaluate each candidate placement solution, and, guide the optimization process. In the case of multi-objective implementations, ultimately offering a realistic perspective of the LDE-aware design tradeoffs between performance deterioration and used chip area. Experimental results conducted over state-of-the-art analog structures on a challenging 65-nanometers technology node show that the proposed methodology shortens the gap between pre- and post-layout performance by reducing the LDE-induced variations, aiming for first-time-right layout design.

Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions

Design productivity remains an important aspect in the analog integrated circuit design industry, as growing competition and shorter design cycles pressure the traditional flow that involves time-consuming manual iterations in a circuit simulator. This paper describes innovations within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop. It lets the designer explore and understand the design space boundaries in a systematic setting, thus supporting informed decision making and architectural innovation that is difficult to attain with fully automated, black-box sizing tools. Our discussion begins with an overview of the LUT-based design paradigm and its two primary variants: inverse design (finding design parameters that meet the specifications) and forward evaluation (sweeping design parameters to search the design space). In support of the latter, the core of our work focuses on improving the accuracy and speed of LUT access, enabling millions of queries within seconds on a standard computer. Large improvements over prior art are enabled using enhanced interpolation methods, which allow for a relatively large LUT grid spacing (hence small memory footprint) and yet accurate parameter lookup. We evaluate the efficacy of the proposed methods using two classical analog circuits, a bandgap reference and a folded cascode amplifier. In the bandgap example, we observe less than 1 ppm error between the LUT-predicted temperature coefficient and circuit simulation. In the folded-cascode example, one million design points are generated in only 4 seconds, providing the designer with useful maps that delineate the reachability of certain target specifications.

Behavior Modeling of the Amplifier Nonlinearity With the AC Josephson Voltage Standard

Behavior models of electronic components are critical in many metrological and measurement areas, e.g., time-domain simulations for analog-integrated circuit design and predistortion of the amplifier to reduce the distortion. This paper describes the use of pulse-driven ac Josephson voltage standard (ACJVS) to synthesize quantum accurate waveforms with ultralow distortion and noise floor to model the amplifier nonlinearity, which is a promising way to increase the modeling accuracy. Four Volterra series models including the memory polynomial model and three submodels of the dynamic deviation reduction model are analyzed and compared in detail. Normalized mean square error is calculated to evaluate the modeling accuracy. The difference of the measured and predicted outputs of the amplifier are compared in both time and frequency domains. The result shows that high-performance models can be achieved, which demonstrates the feasibility of modeling nonlinear amplifier behavior with the ACJVS.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Design techniques for low-voltage analog integrated circuits

Abstract In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Stochastic-based placement template generator for analog IC layout-aware synthesis

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.

Estimating the Impact of Methodology on Analog Integrated Circuit Design Time

The article discusses analog design practices and proposes a project management model for studying which analog design methodology will achieve the fastest time-to-market given the probability of design errors.