Analog Integrated Circuit Design Research Articles

An Integrated Layout-Synthesis Approach for Analog ICs

In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

An Active 2-D Silicon Cochlea

In this paper, we present an analog integrated circuit design for an active 2-D cochlea and measurement results from a fabricated chip. The design includes a quality factor control loop that incorporates some of the nonlinear behavior exhibited in the real cochlea. This control loop varies the gain and the frequency selectivity of each cochlear resonator based on the amplitude of the input signal.

Designing SRCOs by combining SPICE and Verilog-A

The design of single-resistance-controlled oscillators (SRCOs) is presented by using current followers (CF) and voltage followers (VF). First, the design of the followers is described by using SPICE and standard CMOS technology of 0.35 µm. Second, a SRCO is simulated in SPICE by using the designed CF and VF. Third, the SRCO is simulated in Verilog-A by using ideal and real behavioural models for the followers. Finally, the good agreement on the simulation results leads us to conclude on the usefulness to combine SPICE and Verilog-A to enhance analogue integrated circuit design.

Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout

In recent high-performance analog integrated circuit design, it is often required to place some cells symmetrically to a horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement that satisfies the given symmetry constraints and the topology constraints imposed by a sequence-pair (seq-pair). However, this method has the following defects: 1) Balasa's necessary condition for existence of the cell placement that satisfies the given constraints is incorrect; 2) some cells overlap; 3) the closest placement of satisfying both the symmetry and topology constraints is not always obtained; and 4) there is no explanation of placing cells symmetrically to plural axes. In this paper, we clarify the necessary and sufficient conditions for the existence of the cell placement that satisfies the given symmetry constraints and the topology constraints imposed by a seq-pair, and we propose an efficient method of obtaining, by linear programming, the closest cell placement that satisfies the given constraints. Here, a simple constraint graph is obtained from a seq-pair in order to derive a set of linear constraint expressions. Then, to shorten the running time of linear programming, the number of linear expressions is reduced by substituting the expressions for dependent variables, and the solution is obtained. The effectiveness of the proposed method was shown by computational experiments

Communication Scheme for a Highly Collision-Resistive RFID System

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.5 × 10-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.9 × 10-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

Teaching Mixed-Signal Integrated Circuit Design to Undergraduates

A two-course sequence that teaches the basic concepts associated with digital, analog, and mixed-signal integrated circuit design for senior-level undergraduate students has been developed. The use of hands-on experiences using custom integrated circuits is employed to help teach these complex topics. This sequence has been taught for three years, and the affective learning has been assessed through precourse and postcourse surveys, focus groups, and in-class surveys.

SiGe BiCMOS integrated circuits for high-speed serial communication links

Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data- and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10-13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40-56-Gb/s multiplexer/demultiplexer functions and clock-and-data- recovery/clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies.

Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.

Broadband high-frequency hybrid

Analog integrated circuit designs are often differential and require differential-to-single-ended hybrids for spectral measurements. This paper describes a broadband, high-frequency hybrid, whose output signal is proportional to the difference of two input ports, i.e., proportional to the differential signal. The main novelty of this hybrid is its high bandwidth (two to three decades). Such high bandwidth is obtained through combining broadband structures: a pair of broadband impedances are used to scale the two incoming signals; a symmetric structure of two identical broadband directional couplers and a power combiner are used afterwards to obtain the differential signal. The high bandwidths of both the impedances, the directional couplers, and the power combiner make it possible to obtain a differential coupling factor and a common-mode rejection ratio which is frequency insensitive over several decades in frequency. Measurements support the statement that bandwidths of more than three decades can be obtained using the proposed hybrid.

Computer-aided design of analog and mixed-signal integrated circuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

Prolog to computer-aided design of analog and mixed-signal integrated circuits

Prolog to computer-aided design of analog and mixed-signal integrated circuits

Analog integrated circuit design [Book Review

Analog integrated circuit design [Book Review

Novel extension of neu-MOS techniques to neu-GaAs

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in: Proceedings of the 1997 IEEE Custom Integrated Circuits Conference, 1997; B. Gonzales, D. Abbott, S.F. Al-Sarawi, A. Hernandez, J. Garcia, J. López, in: Proceedings of the XIII Design of Circuits and Integrated Systems Conference (DCIS'98), 1998, pp. 62–66]. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, i.e. at the most elemental level in circuits, introduces a degree of flexibility that may lead to the realisation of intelligent functions at a system level [T. Ohmi, T. Shibata, in: Proceedings of the 20th International Conference on Microelectronics, vol. 1, 1995, pp. 11–18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate.

A noise-based IC random number generator for applications in cryptography

The design of a mixed-signal random number generator (RNG) integrated circuit (IC) suitable for integration with hardware cryptographic systems is presented. Certain applications in cryptography require the use of a truly RNG, a device which produces unpredictable and unbiased digital signals derived from a fundamental noise mechanism. For IC-based cryptographic systems, an RNG must harness randomness from a low-power noise signal yet remain insensitive to deterministic influences such as crosstalk, power supply noise, and clock signal coupling through the substrate. An RNG IC utilizing established analog IC design techniques was designed and fabricated in a 2-/spl mu/m CMOS technology. Sequences generated by the experimental system repeatedly passed many standard randomness tests for bit rates up to 1.4 MHz. No changes in randomness performance were observed as the system was exposed to power supply noise and substrate signal coupling. The system occupies a total chip area of 1.5 mm/sup 2/ and dissipates 3.9 mW of power.

Accurate active-feedback CMOS cascode current mirror with improved output swing

An improved active-feedback CMOS cascode current mirror is introduced which has a very accurate current reflection ratio, while achieving the same output impedance as that of an equivalent conventional active-feedback cascode current mirror (CAFCCM) and a wider and optimal output dynamic range. The design can be made with even lower power consumption than CAFCCM and similar chip area. The technique can also be implemented in bipolar and BiCMOS integrated circuit design. The new structure does not need an additional constant current source as CAFCCM does. With these features, the circuit is suitable for use in high precision analogue integrated circuit design; especially in design of currentmode and low-voltage integrated circuits.

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

Book Review: "High-Frequency Analog Integrated Circuit Design", Ravender Goyal (Editor)

Journal of Electronics ManufacturingVol. 06, No. 04, pp. 317 (1996) Book ReviewNo AccessBook Review: "High-Frequency Analog Integrated Circuit Design", Ravender Goyal (Editor)Terry EdwardsTerry EdwardsDepartment of Manufacturing Engineering, Loughborough University, Loughborough, Leics, LE 11 3TU, UKhttps://doi.org/10.1142/S0960313196000263Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail John Wiley & Sons, Inc. 1995 FiguresReferencesRelatedDetails Recommended Vol. 06, No. 04 Metrics History PDF download

Analog IC design automation. I. Automated circuit generation: new concepts and methods

The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Book Review: Design and Applications of Analog Integrated Circuits

Book Review: Design and Applications of Analog Integrated Circuits

Design and performance of semi-custom analog IC including two TACs and two current integrators for 'Super-Kamiokande'

A semicustom analog integrated circuit (IC) has been developed for the front end of the Super-Kamiokande experiment. This IC includes two TACs (time-to-amplitude converters) with 1-ns resolution and two current integrators with 10-bit resolution in a 24-DIP package. In order to reduce the development period and the design effort, a commercial-base bipolar analog gate array was adopted. With this technology, it took only a half year to design and produce the test chips. >