Analog Figures Of Merit Research Articles

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

In this work, a hetero-gate-oxide charge plasma-based nanowire transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the conventional charge plasma-based nanowire transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF)/analog figure of merits. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66 × 108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (g m ) of 3.43 × 10−5 S/μm, and peak cut-off frequency (f t ) of 114 GHz. The simulation employs a comprehensive quantum transport model, and the comparative impacts of adjusting channel length (L g ), nanowire radius (r), and gate oxide thickness (Tox) are studied.

Exploring the efficacy of implementing field plate design with air gap on β-Ga2O3 MOSFET for high power & RF applications

In the present work, source field plate design with an air gap has been studied on lateral β – Ga2O3 MOSFET with the objective of achieving improvement in high power as well as RF performance by employing exhaustive TCAD simulations. A comprehensive investigation of various analog Figure of Merits (FoMs) and RF Figure of merits (FoMs) have been carried out and a thorough comparison has been drawn between the proposed device β-Ga2O3 MOSFET with source field plate and air gap, the β-Ga2O3 MOSFET with gate field plate and the conventional β-Ga2O3 MOSFET. It can be noted that the proposed design yields significantly higher breakdown voltage and Power Figure of Merit (PFoM) as compared to gate field plate design and conventional device without any of these designs and also, the proposed design demonstrates improvement in RF performance as compared to gate field plate design.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

AbstractNegative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different DC and analog figure of merits such as on current (), switching ratio (), threshold voltage roll‐off, sub‐threshold swing (SS), trans‐conductance (), transconductance efficiency () of the test device has been analyzed for different ferroelectric layer thicknesses and compared with the baseline device. We have investigated RF performance such as gate capacitance, unity‐gain cut‐off frequency and small signal voltage gain of the device. Improvement in DC and analog figure of merits is proportional to the ferroelectric layer thickness. However, for higher values of ferroelectric thickness, the hysteresis effect gradually became prominent. MOS transistor with optimum ferroelectric layer thickness shows the negligible amount of threshold voltage roll‐off and improved transconductance‐frequency product compared to the baseline device. In presence of ferroelectric layer, the effect of channel thickness variation on device performance is reduced. The role of ferroelectric gate stack is found to be more prominent at shorter gate length.

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

AbstractThis paper proposes a dual metal gate, hetero‐material tunneling interfaced junctionless tunnel field effect transistor (TFET), (DMG‐HJLTFET), utilizing III–V compound semiconducting materials, InAs (low band‐gap source material)/GaAs (higher band‐gap channel and drain material) by applying the band‐gap and dual material gate engineering. The 2‐D TCAD simulations have been executed to explore the impact of tunnel gate process variations—work function and length on DC and analog figure of merits (FOMs) of DMG‐HJLTFET. The extracted result parameters have also been compared to SMG (single metal gate)‐HJLTFET and conventional Si‐JLTFET. The DMG‐HJLTFET attains improved ON current in the range of 88.5 × 10−6 A/μm and OFF current remains as low as 2.89 × 10−16 A/μm. It exhibits a high current switching ratio of 3.1 × 1011 as compared to SMG‐HJLTFET (ION = 24 × 10−6 A/μm and ION/IOFF = 1.4 × 1011) and Si‐JLTFET (ION = 7 × 10−6 A/μm and ION/IOFF = 1.8 × 106). Further, the radio frequency/microwave (RF) parameters such as power gains (h12, UPG, and Gma), fmax, and GBP have been compared for all three aforementioned devices. Moreover, the small signal admittance (Y) parameters have been examined to explore the possible scope of DMG‐HJLTFET for future internet of everything communications and fast switching applications.

Device-circuit analysis of ultra-thin body In1−x Ga x As on insulator MOS transistor with varying indium mole fraction and channel thickness

In this paper, with the help of a well-calibrated simulation study, we explore the design space of ultra-thin body In1−x Ga x As-on-Insulator MOS transistor. We have studied the effect of Indium content, and channel thickness on carrier mobility, different analog figure of merits such as transconductance, transconductance generation factor, output conductance, and intrinsic gain of UTB III–V on Insulator MOS transistor. Moreover, we have analyzed the RF performance of the device in terms of unity gain cut-off frequency and maximum oscillation frequency. To verify frequency response characteristics and DC transfer characteristics, the circuit implementation of the UTB III–V on Insulator MOS transistor was performed on a cascode amplifier and differential amplifier. Our result shows that while increasing channel thickness and Indium content, the carrier transport property of the device improves. With an increase in channel thickness and Indium content, a significant improvement in carrier mobility is observed. Due to the poor electrostatic integrity, off-state current of the device increases with channel thickness and Indium content. Due to enhanced transport property, drain current, transconductance, unity gain cut-off frequency, and maximum oscillation frequency also improve. The improvement in analog and RF figure of Merits are also reflected in circuit performance.

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

This paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device’s analog figures of merit. Also, it has been analyzed the DIBL, GIDL, Ion, and Ioff. currents.

Performance Evaluation of 10nm SMG FinFET with Architectural Variation towards DC/RF and Temperature Aspects

FinFET structures of 10 nm technology node with promising design enhancements like hybrid spacer, raised source and drain extensions, and silicide interfaces have been analysed and compared. Analog figures of merit like drain current, transconductance, intrinsic gain, and transconductance generation factor are determined here. Furthermore, RF figures of merit like cut-off frequency, intrinsic delay, and gate capacitance are analysed. These parameters have been determined at three different temperatures (200 K, 300 K, 400 K) to study the effect of temperature on device performance.

Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Quadruple gate FinFET is a promising candidate among other multi-gate MOS devices due to it’s better scalability and higher short channel effect suppression capability in advanced technology node. In this work, we report the effect of temperature on various performance metrics of quadruple gate FinFET like electrostatic integrity, carrier mobility, switching ratio, analog/RF, and linearity parameters with the help of well-calibrated numerical device simulation-based study (TCAD). While increasing the temperature from 250 °K to 450 °K, due to the enhanced bulk phonon scattering, degradation in carrier effective mobility is observed. Sub-threshold swing and drain induced barrier lowering coefficient vary linearly with temperature. At high temperature, due to the reduced carrier mobility, degradation in the analog figure of merits is observed. RF performance parameters also degrade primarily due to the enhanced gate capacitance and reduced trans-conductance. However, some linearity parameter improves at high temperature due to the reduced magnitude of the higher-order derivative of trans-conductance. Another major contribution of this work is, we demonstrate the inflection point or temperature compensation point in some analog/RF performance metrics where the device characteristics almost invariant with temperature.

Effects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis

In this article, the combined effect of BOX thickness (TBOX) and ground-plane (GP) doping (NGP) on channel carrier mobility and analog figures of merit (FoMs) is investigated. It is reported that the thin BOX along with higher NGP will limit the electron/hole mobility of ultrathin body and BOX fully depleted silicon-on-insulator (UTBB FD-SOI) MOS transistors. The physics responsible for this observation is discussed in detail. The contrasting behavior of different GPs, the effect of TBOX scaling, and gate-length scaling on device behavior is also analyzed. It is also shown that in advanced UTBB FD-SOI MOS transistors, a tradeoff exists between transistor intrinsic gain, cutoff frequency, and non-linearity. In nMOS transistors, the best intrinsic gain and cut-off frequency can be achieved with ultrathin BOX and n-type GP (or with no GP), whereas the best linearity can be achieved with ultrathin BOX and p-type GP implant.

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications

A simple continuous analytical model is developed for the drain current of unipolar junction dual material double gate MOSFET (UJDMDG). The model is based on electrostatic potentials obtained from the solution of Poisson’s equation using parabolic approximation method, surface potential, electric field, threshold voltage roll-off and drain current are explicitly modelled. Analytical results are verified and validated by comparing it with the result obtained from Silvaco TCAD ATLAS device simulator making it suitable for circuit design simulations. A comparative study of the short-channel effects (SCEs) for UJDMDG and unipolar junction single material double gate MOSFET (UJSMDG) structures has been carried out in order to show the efficacy of gate material engineering to suppress SCEs. Moreover, the variation of RF and analog figure of merits as a function of downscaled gate lengths has been reported. To exhibit the superiority in RF/analog performance of UJDMDG over UJSMDG MOSFETs, the analog/RF performance parameters has been studied and compared for SoC applications.

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs.

The analog figure-of-merits (FOMs) of conventional inversion-mode (IM) and junctionless (JL) NanoWire Field Effect Transistor (NWFET) have been investigated, considering the gate Work-Function Variability (WFV) and Random Discrete Dopant (RDD) using 3-dimensional (3D) TCAD simulation. While the JL-NWFET shows higher immune to WFV on analog FOMs, it can be easily affected by RDD due to higher channel doping level. On the other hand, the IM-NWFET shows stronger correlation between transconductance (gm) and gate capacitance (Cgg), leading to similar variation in cut-off frequency (ft) even though it shows larger gm and Cgg variation compared to JL-NWFET.

Tunnel FET Analog Benchmarking and Circuit Design

A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinFET technology at the 14-nm node. This benchmarking is enabled by the development of a universal TFET SPICE model and a parameter extraction procedure based on data from physics-based device simulators. Analog figures of merit are computed versus current density to compare TFETs with CMOS for low-power analog applications to reveal promising directions for the system development. To illustrate the design space enabled by TFETs featuring sub-60-mV/decade subthreshold swing, two example circuits including a picopower common-source amplifier and an ultralow-voltage ring oscillator are demonstrated.

Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .

Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations

In this paper, analog/RF performance of source side only dual-k spacer (Dual-kS) trigate junctionless transistor (JLT) is investigated with respect to the parametric variations. It is observed that the Dual-kS JLT improves analog/RF figure of merits (FOMs) and shows its lower dependence to the parametric variations compared with the conventional (low-k spacer) JLT. This study reveals that the design of Dual-kS JLT with lower aspect ratio (1–3) improves the analog FOMs with moderate frequency of operations at fin-width of 10 nm with gate length being 20 nm. Moreover, the frequency of operation can be increased further by increasing the aspect ratio (4–6) without sacrificing the analog FOMs such as transconductance (gm), output conductance (gds) and intrinsic voltage gain (AV0). It is also reported that gds of Dual-kS JLT is least sensitive to the variation in fin-width, doping concentration and oxide thickness, which proves the potential of Dual-kS device to act as a constant current source. Moreover, Dual-kS device is found to be robust against the variation in doping concentration and oxide thickness, which further improves the merit of Dual-kS JLT for low-voltage/low-power analog/RF applications.

A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications

The double-gate (DG) metal-oxide-semiconductor field effect transistors (MOSFETs) are the choice of technology in sub -100 nm regime of leading microelectronics industry. To enhance the analog and RF performance of DG MOSFET, an underlap dual-material (DM) DG MOSFET device structure has been considered because, it has the advantages of both underlap as well as that of dual-material gate (DMG). A 2D analytical surface potential, subthreshold current, subthreshold swing as well as transconductance modelling of underlap DMDG MOSFET has been done by solving the Poisson's equation. It has also been found that, numerically simulated data approves the analytically modelled data with commendable accuracy. As underlap length (Lun) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. DMG structure facilitates to improve the average velocity of carriers which leads to superior drive current of the device. The underlap DMDG MOSFET device structure demonstrates an ameliorated subthreshold characteristic. The analog figure of merits (FOMs) such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (AV) and RF FOMs namely cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP) and gain transconductance frequency product (GTFP) have been evaluated. The aforesaid analysis revels that, the device is best suited for communication related Analog/RF applications.

Germanene nanoribbon tunneling field effect transistor (GeNR-TFET) with a 10 nm channel length: analog performance, doping and temperature effects

In this paper, a scheme of the germanene nanoribbon tunneling field effect transistor (GeNR-TFET) is proposed. The characteristics and analog performance of the device were theoretically investigated by exploiting the electrical properties of a germanene nanoribbon and applying the doping concentration in the source and drain regions at 300 K and 4 K temperatures. The device parameters were obtained using a non-equilibrium Green’s function (NEGF) method within the tight binding (TB) Hamiltonian. The TB Hamiltonian was extracted from the density functional theory (DFT) through the Wannier function. We find that by increasing the doping concentration the Ion current increases which leads to an improvement of the Ion/Ioff ratio to 105. Moreover, decreasing the temperature from 300 K to 4 K causes the Ioff to become ten times smaller. We find that the device output characteristic displays a negative differential conductance with a good peak-to-valley ratio which is improved by increasing the doping concentration. The analog performance of the device is also investigated in the subthreshold regime of operation by varying the doping concentration. It is observed that by increasing the device doping concentration, the analog figures of merit can be improved.

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

In this paper, δ-doped partially insulated junctionless transistor (δ-Pi-OXJLT) has been proposed which shows that, employing highly doped δ-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed δ-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed δ-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed δ-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed δ-Pi-OXJLT clearly shows that the proposed δ-Pi-OXJLT is the promising device for mixed signal integrated circuits.