Analog Domain Research Articles

Transmit Beamforming for Communication and Self-Interference Cancellation in Full Duplex MIMO Systems: A Trade-Off Analysis

The performance of transmit beamforming for both optimized precoding and self-interference cancellation (SIC) in full duplex multiple input multiple output (MIMO) transceivers is analysed in this paper. With sub-space dimension larger than that of the null-space of the self-interference channels, the precoding error is reduced but the interference suppression ratio (ISR) is degraded, resulting in a trade-off between multibeam communication and MIMO SIC. An analytical approach for the ISR evaluation is proposed assuming known eigenvalue distribution of the self-interference channels, and a closed-form ISR expression is derived after applying a uniform distribution approximation. The ISR and precoding error trade-off curves are also formulated. Joint SIC by transmit beamforming and beam-based analog adaptive filters over both propagation and analog domains is proposed to achieve better SIC performance and enable more flexible receive antenna selection. Simulation results verify the theoretical analyses.

Fully Integrated Analog Machine Learning Classifier Using Custom Activation Function for Low Resolution Image Classification

This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing down-sampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is $3\times $ better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from $28\times 28$ pixels to $5\times 5$ pixels.

All-Pass Frequency Selective Structures: Application for Analog Domain

Two new simple and effective voltage mode frequency selective structures that pass all signals are proposed and explored in this paper. The proposed structures use a single active element and three passive components in each. Dual-X second generation current conveyor (DXCCII) is employed as an active element along with two resistors and a capacitor as passive elements. The capacitor is grounded which goes well with the IC fabrication requirements. Both the structures offer low active and passive sensitivities. The presented structures also exhibit the feature of high input impedance. A comprehensive study of device non-idealities and parasitic is also included to highlight the non-ideal performance of the presented ideas. In addition, to prevent the use of passive resistors, resistor less realizations of proposed structures are also explored by replacing the passive resistors with MOS-based active resistors. A quadrature oscillator is also presented as one of the possible applications of the proposed frequency selective structures. Simulations results are in match with the theoretically analyzed performance.

Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals

Processing-in-memory (PIM) architectures have demonstrated great potential in accelerating numerous deep learning tasks. Particularly, resistive random-access memory (RRAM) devices provide a promising hardware substrate to build PIM accelerators due to their abilities to realize efficient in-situ vector-matrix multiplications (VMMs). However, existing PIM accelerators suffer from frequent and energy-intensive analog-to-digital (A/D) conversions, severely limiting their performance. This paper presents a new PIM architecture to efficiently accelerate deep learning tasks by minimizing the required A/D conversions with analog accumulation and neural approximated peripheral circuits. We first characterize the different dataflows employed by existing PIM accelerators, based on which a new dataflow is proposed to remarkably reduce the required A/D conversions for VMMs by extending shift and add (S+A) operations into the analog domain before the final quantizations. We then leverage a neural approximation method to design both analog accumulation circuits (S+A) and quantization circuits (ADCs) with RRAM crossbar arrays in a highly-efficient manner. Finally, we apply them to build an RRAM-based PIM accelerator (i.e., \textbf{Neural-PIM}) upon the proposed analog dataflow and evaluate its system-level performance. Evaluations on different benchmarks demonstrate that Neural-PIM can improve energy efficiency by 5.36x (1.73x) and speed up throughput by 3.43x (1.59x) without losing accuracy, compared to the state-of-the-art RRAM-based PIM accelerators, i.e., ISAAC (CASCADE).

Vector Modulator-Based Analog Beamforming Using the Least Euclidean Distance Criterion

In traditional multiple-input multiple-output (MIMO) receivers, radio frequency (RF) front-ends are exposed to interference as no analog spatial filtering is employed before the digital beamforming stage. Therefore the RF front-end is power-hungry, and analog to digital converters require a high dynamic range. In this paper, we consider an analog beamforming system in case of narrowband signals to cancel interference early in the analog domain, thus reducing the required ADC resolution. In contrast to existing analog beamformers with only phase shifts, our proposed design employs vector modulators where the coefficients can be selected from a set of weights with variable phases and amplitudes. We also propose an efficient and fast Euclidean distance algorithm to determine the analog beamformer coefficients while being suitable for realistic scenarios. Finally, an expression is introduced to estimate the interference rejection achieved by employing the proposed algorithm and a vector modulator in the RF domain. The introduced algorithm leads to considerable improvement in computational complexity by slightly sacrificing interference rejection.

Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning. The input vector and weight matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed in the analog domain within memory sub-array, leading to significant improvements in throughput and energy efficiency. Static random access memory (SRAM) and emerging non-volatile memories such as resistive random access memory (RRAM) are promising candidates to store the weights of deep neural network (DNN) models. In this review, firstly we survey the recent progresses in SRAM and RRAM based CIM macros that have been demonstrated in silicon. Then we discuss general design challenges of the CIM chips including analog-to-digital conversion (ADC) bottleneck, variations in analog compute, and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework that is capable of evaluating versatile device technologies for CIM inference and training performance from software/hardware co-design's perspective.

Construction of Golay Complementary Matrices and Its Applications to MIMO Omnidirectional Transmission

Golay complementary sequences (GCS) have found wide applications in radar and communications thanks to their prominent property of complementary autocorrelation. This paper studies the extension of Golay complementary sequences to Golay complementary matrices (GCM), i.e, a pair of matrices whose two-dimensional autocorrelations add to be a two-dimensional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\delta$</tex-math></inline-formula> -function. While the construction of (real) binary GCM are available in the literature, how to construct the quaternary GCM (and the more general unimodular GCM) remains unknown. We put together this missing piece, and show the feasible size that allows for binary and quaternary GCM. The feasible sizes can be further expanded if the phases of the matrices’ entries can be arbitrary. In addition, we consider the extension of the GCM to the set of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N$</tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N\geq 2$</tex-math></inline-formula> ) matrices, whose two-dimensional autocorrelations add to be a two-dimensional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\delta$</tex-math></inline-formula> -function, which we refer to as autocorrelation complementary matrices (ACM). For <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N=4$</tex-math></inline-formula> , the ACM allows for matrices of arbitrary size. The GCM/ACM can be applied to omnidirectional transmission for a multi-input multi-output (MIMO) communication system with a uniform rectangular array (URA), which is useful for broadcasting cell-wide common messages. We propose two schemes for omnidirectional transmission, one is based on space-time block code (STBC) and the other is based on the dual cross-polarization of the antenna array. Both schemes can be implemented in the radio frequency (RF) analog domain, generating (theoretically) perfect omnidirectional beampattern with low hardware cost.

Wideband User Grouping for Uplink Multiuser mmWave MIMO Systems With Hybrid Combining

Analog-digital hybrid precoding and combining schemes constitute an interesting approach to millimeter-wave (mmWave) multiple-input multiple-output (MIMO) systems due to the low hardware complexity and/or low power required for its deployment. However, the design of the hybrid precoders and combiners of a wideband multiuser (MU) mmWave MIMO system is challenging because the signal processing in the analog domain is constrained to be frequency flat. Furthermore, the number of radio frequency (RF) chains limits the number of individual streams that a common base station (BS) can simultaneously serve. This work jointly addresses the user scheduling, the user precoder design, and the BS hybrid combining design for the uplink of wideband MU mmWave MIMO systems. On the one hand, user precoding and BS hybrid combining are jointly designed to minimize the impact of having frequency-flat RF components. On the other hand, a number of users larger than the number of RF chains are served at the BS by employing a distributed quantizer linear coding (DQLC)-based non-orthogonal multiple access (NOMA) scheme. The use of this encoding strategy also allows exploiting the spatial correlation between the source information. Simulation results show remarkable performance gains of the proposed approaches for wideband mmWave MIMO hardware-constrained systems.

Hybrid Precoding Algorithm for Millimeter‐Wave Massive MIMO Systems with Subconnection Structures

In mmWave massive MIMO systems, traditional digital precoding is difficult to be implemented because of the high cost and energy consumption of RF chains. Fortunately, the hybrid precoding which combines digital precoding and analog precoding not only solves this problem successfully, but also improves the performance of the system effectively. However, due to the constant mode constraint introduced by the phase shifter in the analog domain, it is difficult to solve the hybrid precoding directly. There is a solution which divides the total optimization problem into two stages to solve, that is, first fix the digital precoding matrix, solve the analog precoding matrix, and then optimize the digital precoding matrix according to the obtained analog precoding matrix. In this paper, a high energy‐efficient hybrid precoding scheme is proposed for the subconnection structure. In the first stage, the optimization problem can be decomposed into a series of subproblems by means of the independent submatrix structure of the analog precoding matrix. When the optimized analog precoding matrix is obtained, the digital precoding matrix can be solved by the minimum mean error (MMSE). Finally, the digital precoding matrix is normalized to satisfy the constraint conditions. The simulation results demonstrate that the performance of the proposed algorithm is close to that of fully digital precoding based on subconnection structure and better than that of the existing algorithms. In addition, this paper presents the simulation analysis of the algorithm performance under imperfect channel state information. Simulation results show that when the estimation accuracy of channel state information is 0.8, the spectral efficiency of the proposed algorithm can already be maintained at a good level.

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution - or mean propagation delay from one CC element to the next - to be 4.91±0.04 ps (4.54±0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision - or mean error on the timing of the waveform - to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 ± 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating our design’s hardware primitives in an Appendix, and make our FPGA interfacing methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga .

On Full-Duplex Radios With Modulo-ADCs

Wireless full-duplex (FD) transceivers have become more commonplace in the recent years, enabled by improvements in hardware as well as in signal processing algorithms dedicated to self-interference (SI) mitigation. A key design target for any FD radio is to limit the analog-to-digital converter (ADC) quantization noise affecting the signal of interest (SoI), which results from the difference in dynamic range between the SI and the SoI at the input of the ADC. Indeed, when using conventional ADCs, since the SI power is much larger than that of the SoI, the SI spans most of the ADC's dynamic range and the SoI becomes distorted by a large quantization noise. Reducing the power of the SI before the ADC, for example via analog domain SI cancellation, is so far the only means to mitigate this undesired effect. In this paper we consider the use of so-called modulo ADCs as a new tool to reduce the quantization noise that affects the SoI in the presence of SI. We demonstrate theoretically and numerically that by substituting the conventional ADCs with modulo-ADCs, which fold the analog input signal before analog-to-digital conversion, and by using appropriately designed analog gain control and digital-domain SI cancellation, one can reduce the quantization noise that affects the SoI. As such, the work in this paper provides a new technique for counteracting the detrimental effect of SI in analog-to-digital conversion and, thus, provides a new route to be explored in order to enhance the performance of FD radios.

Two-Dimensional Channel Parameter Estimation for Millimeter-Wave Systems Using Butler Matrices

In this paper, a novel two-dimensional parameter estimation method is proposed for frequency-selective millimeter-wave (mmWave) channels by probing a limited number of Kronecker products of discrete Fourier transform (DFT) beams, which are efficiently implemented in the analog domain by a novel combination of Butler matrices. The proposed strategy firstly estimates the channel parameters by using a modified parameter estimation via interpolation based on a DFT grid (PREIDG) algorithm. In a second step, high-resolution channel parameter estimation is achieved even in the low signal-to-noise-ratio (SNR) using the space-alternating generalized expectation-maximization (SAGE) algorithm. The proposed modified PREIDG algorithm outperforms state-of-the-art methods, e.g., the auxiliary beam pair (ABP) method while the SAGE algorithm achieves the derived Cramér-Rao lower bound (CRLB). Numerical results demonstrate that excellent estimation performance can be achieved for angle of departure (AoD) azimuth and elevation with addition to delay and complex path gain of each path even in the low SNR regime.

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-digital-converter (ADC) in the RX AFE has an embedded 2-tap analog feed-forward equalizer. The design objective is to optimize the energy efficiency for the target data rate and the moderate-loss channel. For this purpose, the optimum modulation order that has the least ISI sensitivity for the given equalization capability is decided with a modeling study. All the equalization is performed in the analog domain to avoid the circuit complexity and power consumption disadvantages of the digital equalization in the selected high-order modulation. Thanks to the spectral efficiency of PAM-16 and the analog-only equalization, the figure-of-merit is improved significantly. Post-layout simulations show that the TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 32 Gb/s with PAM-16, which corresponds to 2.38 pJ/bit for the whole system.

Development of Jump Markovian Dynamic Models of Low Cost Digital Duty-Cycle Modulation Drivers For Target System-on-Chip Devices

In this paper, a novel building algorithmic scheme of DDCM (duty-cycle modulation) drivers is presented. It is modelled in the analog domain as a continuous time jump Markovian dynamic model, with a deterministic two-state Markov chain. An equivalent discrete jump dynamic model is computed using pole-zero matching transform. Then, the resulting digital iterative algorithm, consists of simple digital operators and structures. The proposed DDCM algorithm is simulated under Matlab framework, and implemented using Arduino IDE-C++ with uploading into an ESP32 system-on-chip (SoC) device. The monitoring device connected to the ESP32 via an USB communication cable is an Arduino/IDE virtual monitor. It is configured for 230400 bauds communication. A low cost ESP32-based DAC (digital-to-analog converter), is virtually implemented and well tested as a case study of the proposed new generation of DDCM drivers. Matlab digital simulation results and ESP32 processing and virtual monitoring results are presented and discussed, in order to show the realistic nature and the great challenge the proposed DDCM algorithmic scheme for SOC devices.

On the Solvability of the Peak Value Problem for Bandlimited Signals With Applications

In this paper we study from an algorithmic perspective the problem of finding the peak value of a bandlimited signal. This problem plays an important role in the design and optimization of communication systems. We show that the peak value problem, i.e., computing the peak value of a bandlimited signal from its samples, can be solved algorithmically if oversampling is used. Without oversampling this is not possible. There exist bandlimited signals, for which the sequence of samples is computable, but the signal itself is not. This problem is directly related to the question whether there is a link between computability in the digital domain and the analog domain, and hence to a fundamental signal processing problem. We show that there is an asymmetry between continuous-time and discrete-time computability. Further, we study the decay behavior of computable bandlimited signals, which describes the concentration of the signals in the time domain, and, for locally computable bandlimited signals, we analyze if it is always possible to decide algorithmically whether the peak value is smaller than a given threshold.

Designing Mixed-Signal Programmable Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies

A digitally programmable analog Fuzzy Logic Controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimization of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: a 2.7% RMSE, from 2.22 to 5.26 Mflips (Mega fuzzy logic inferences per second) at the pin terminals (@CL=13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL≤ 5pF) up to 8 Mflips may be expected.

CMOS Full-Duplex Mixer-First Receiver With Adaptive Self-Interference Cancellation

A full-duplex transceiver with on-chip self-interference-cancellation (SIC) is presented. The achieved SIC is 110 dB, and it is realized in three stages: RF front-end hybrid, baseband analog, and baseband digital. An integrated hybrid is used in the RF front-end which employs an adaptive tuning impedance network (TIN) to track the antenna impedance variations, achieving over 50 dB of SIC. N-path mixer-first architecture is used for the receiver to improve the linearity and to provide out of band blocker cancellation. The self-interference is further attenuated in the analog domain using the down-converted sample of the transmit signal. The analog transmit interference canceler (TIC) receives the sampled copy of the transmitted signal of the power amplifier and offers adaptive amplitude and phase adjustment for the cancellation signal, obtaining more than 20 dB on-chip cancellation in the analog domain. The last step of SIC is realized in the digital domain using a nonlinear system with memory to cancel the remnant of self-interference and distortions, resulting in 43 dB of SIC. The front-end hybrid, mixer-first receiver, and analog TIC are implemented in a CMOS 65-nm technology. Thanks to adaptive gradient decent algorithm employed in the system, the total SIC of the hybrid and TIC is more than 70 dB, which is one of the highest cancellation values achieved on the chip. The die area is 4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the fabricated chip consumes 80 mW dc power. The average transmit power is 23 dBm, and the noise figure of the receiver in the full-duplex mode is 11 dB.

Stereoselective Synthesis of Spiroacetal Domain Derivatives of the Plant Glycoside Ranuncoside and of Okadaic Acid and Dinophysistoxins-1 and 2 From Marine Algae

Spiroacetals constitute the central structural core element of numerous natural products and are mostly represented as bicyclic or tricyclic domains. Typical natural products with tricyclic spiroacetals are (+)-ranuncoside 1, a glycoside isolated from plants of the Ranuncalaceae family, and the algal toxins (+)-okadaic acid 2 and the (+)-dinophysistoxins-1 and 2 (3 and 4). These substances possess a spiro furan-dioxane-pyran ring system 5 and a spiro furan-pyran-pyran scaffold 6, which are both essential for biological activity. Corresponding analogs with spiro furan-dioxane-cyclohexane framework 7 or ( ent)-7 have so far neither been found in living organisms nor been synthesized. To close this gap and to generate candidates for structure-activity relationship studies which could lead to the discovery of novel antibiotics and selective anticancer agents, we have developed an efficient and stereocontrolled synthetic route to analogous domains of the above natural products. Pyran-dioxane-cyclohexane tricycles 12, 17, and 25 were used as starting materials and, via ring contraction, yielded the 2 derivatives 16 and 29, with spiro ( R)- and spiro ( S)-configuration and tricyclic ring system 7 and ( ent)-7, respectively. The stereochemistry and conformation of all novel products were solved by nuclear magnetic resonance spectroscopy.

Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity

Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on the circuit linearity performance, in analog and RF domains. In this paper, we have proposed a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided. Effect of corner radius has also been included.

Analog Lagrange Coded Computing

A distributed computing scenario is considered, where the computational power of a set of worker nodes is used to perform a certain computation task over a dataset that is dispersed among the workers. Lagrange coded computing (LCC), proposed by Yu et al. , leverages the well-known Lagrange polynomial to perform polynomial evaluation of the dataset in such a scenario in an efficient parallel fashion while keeping the privacy of data amidst possible collusion of workers. This solution relies on quantizing the data into a finite field, so that Shamir’s secret sharing, as one of its main building blocks, can be employed. Such a solution, however, is not properly scalable with the size of dataset, mainly due to computation overflows. To address such a critical issue, we propose a novel extension of LCC to the analog domain, referred to as analog LCC (ALCC). All the operations in the proposed ALCC protocol are done over the infinite fields of ${ \mathbb R}/ { \mathbb C}$ but for practical implementations floating-point numbers are used. We characterize the privacy of data in ALCC, against any subset of colluding workers up to a certain size, in terms of the distinguishing security (DS) and the mutual information security (MIS) metrics. Also, the accuracy of outcome is characterized in a practical setting assuming operations are performed using floating-point numbers. Consequently, a fundamental trade-off between the accuracy of the outcome of ALCC and its privacy level is observed and is numerically evaluated. Moreover, we implement the proposed scheme to perform matrix-matrix multiplication over a batch of matrices. It is observed that ALCC is superior compared to the state-of-the-art LCC, implemented using fixed-point numbers, assuming both schemes use an equal number of bits to represent data symbols.