Analog Circuits Research Articles

Detecting and Classifying Parametric Faults in Analog Circuits Using an Optimized Attention Neural Networks

Detecting and Classifying Parametric Faults in Analog Circuits Using an Optimized Attention Neural Networks

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

A Concise 4D Conservative Chaotic System with Wide Parameter Range, Offset Boosting Behavior and High Initial Sensitivity

In this paper, we present a concise four-dimensional (4D) conservative chaotic system with a wide parameter range. Since there are no terms higher than first order, the circuit does not contain multipliers, resulting in a simple circuit implementation. The nonlinear dynamic characteristics, such as phase diagrams, equilibrium points, divergence, Poincaré cross-sections, Lyapunov exponents, bifurcation diagrams, and Lyapunov dimension, are analyzed in detail, which illustrates the conservativity. Besides, the system exhibits different offset boosting behaviors. Through offset boosting, the system can propagate along a line, convert signal polarity, control variable amplitude, generate coexisting attractors, and even induce changes in its state. Specially, we realize the transition from a single-vortex attractor to a multivortex one by some changes in the initial values. Furthermore, the Pearson correlation coefficient is used to demonstrate the higher initial value sensitivity of the system. Finally, the system is implemented through Multisim simulation and analog circuit separately, and their consistency validates the system effectively.

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

Neuromorphic place cells

A neuromorphic simultaneous localization and mapping (SLAM) system shows potential for more efficient implementation than its traditional counterpart. At the mean time a neuromorphic model of spatial encoding neurons in silicon could provide insights on the functionality and dynamic between each group of cells. Especially when realistic factors including variations and imperfections on the neural movement encoding are presented to challenge the existing hypothetical models for localization. We demonstrate a mixed-mode implementation for spatial encoding neurons including theta cells, egocentric place cells, and the typical allocentric place cells. Together, they form a biologically plausible network that could reproduce the localization functionality of place cells observed in rodents. The system consists of a theta chip with 128 theta cell units and an FPGA implementing 4 networks for egocentric place cells formation that provides the capability for tracking on a 11 by 11 place cell grid. Experimental results validate the robustness of our model when suffering from as much as 18% deviation, induced by parameter variations in analog circuits, from the mathematical model of theta cells. We provide a model for implementing dynamic neuromorphic SLAM systems for dynamic-scale mapping of cluttered environments, even when subject to significant errors in sensory measurements and real-time analog computation. We also suggest a robust approach for the network topology of spatial cells that can mitigate neural non-uniformity and provides a hypothesis for the function of grid cells and the existence of egocentric place cells.

SnS2 memtransistor-based Lorenz chaotic system for true random number generation

As the Internet of Things (IoT) landscape expands, the need for robust and energy-efficient hardware security has increased. In this study, we demonstrate a novel true random number generation (TRNG) system that combines a tin disulfide (SnS2) nanosheet-based memtransistor with the Lorenz chaotic system. This synergy leverages the intrinsic stochasticity of electron trapping at the SnS2 interfaces and the energy efficiency of the Lorenz chaotic system realized by an analog circuit. In addition, we provide a comprehensive evaluation of the energy consumption of the entire TRNG system based on direct measurements of the supply current. Remarkably, our TRNG achieves an energy consumption of 4.3 μJ/bit with a throughput of 10 kbit/s.

Integration of MoS2 Memtransistor Devices and Analogue Circuits for Sensor Fusion in Autonomous Vehicle Target Localization.

In contemporary autonomous driving systems relying on sensor fusion, traditional digital processors encounter challenges associated with analogue-to-digital conversion and iterative vector-matrix operations, which are encumbered by limitations in terms of response time and energy consumption. In this study, we present an analogue Kalman filter circuit based on molybdenum disulfide (MoS2) memtransistor, designed to accelerate sensor fusion for precise localization in autonomous vehicle applications. The nonvolatile memory characteristics of the memtransistor allow for the storage of a fixed Kalman gain, which eliminates the data convergence and thus accelerates the processing speeds. Additionally, the modulation of multiple conductance states by the gate terminal enables fast adaptability to diverse autonomous driving scenarios by tuning multiple Kalman filter gains. Our proposed analogue Kalman filter circuit accurately estimates the position coordinates of target vehicles by fusing sensor data from light detection and ranging (LiDAR), millimeter-wave radar (Radar), and camera, and it successfully solves real-word problems in a signal-free crossroad intersection. Notably, our system achieves a 1000-fold improvement in energy efficiency compared to that of digital circuits. This work underscores the viability of a memtransistor for achieving fast, energy-efficient real-time sensing, and continuous signal processing in advanced sensor fusion technology.

A phase modulation method of sine signal for dual-active-valve piezoelectric pump

A phase modulation method with wide range and high resolution for the sine signal is essential for dual-active-valve piezoelectric pump (DAVPP) control. In DAVPP, by phase modulation, the flow direction can be changed and the output flow rate and pressure can be precisely adjusted. In this article, the authors developed a phase modulation method for the sine signal. This method is characterized by both the combination of hardware and software, and the combination of digital circuits and analog circuits. In hardware, a sinxcosϕ constructing circuit and a cosxsinϕ constructing circuit are specially structured, which enables phase modulation to be achieved. In software, the output phase is determined by the digital controlling quantities sent by the main control chip and stored in the form of a table. Analytical formulas for the cosine constructing table tab_cos and the sine constructing table tab_sin are analyzed and structured. Experimental results show that the output phase can be regulated linearly and continuously, within a range of 0°–360°. Its resolution can be improved according to the requirements. Although the modulation process and circuit are simple, it can effectively solve the problem of sine signal phase modulation for DAVPP control.

Highly-integrable analogue reservoir circuits based on a simple cycle architecture

Physical reservoir computing is a promising solution for accelerating artificial intelligence (AI) computations. Various physical systems that exhibit nonlinear and fading-memory properties have been proposed as physical reservoirs. Highly-integrable physical reservoirs, particularly for edge AI computing, has a strong demand. However, realizing a practical physical reservoir with high performance and integrability remains challenging. Herein, we present an analogue circuit reservoir with a simple cycle architecture suitable for complementary metal-oxide-semiconductor (CMOS) chip integration. In several benchmarks and demonstrations using synthetic and real-world data, our developed hardware prototype and its simulator exhibit a high prediction performance and sufficient memory capacity for practical applications, showing promise for future applications in highly integrated AI accelerators.

An analog circuit fault diagnosis method using improved sparrow search algorithm and support vector machine.

In analog circuits, component tolerances and circuit nonlinearity pose obstacles to fault diagnosis. To solve this problem, a soft fault diagnosis method based on Sparrow Search Algorithm (SSA) and Support Vector Machine (SVM) is used. In this study, ISSA is obtained by optimization using four strategies for SSA deficiency. Twenty-three benchmark functions are used for optimization experiments, and ISSA converges faster, more accurately, and with better robustness than other swarm intelligence algorithms. Finally, ISSA is used to optimize the SVM parameters and establish the ISSA-SVM fault diagnosis model. In the Sallen-key test circuit diagnosis experiments, the correct fault diagnosis rates of SSA-SVM and ISSA-SVM are 97.41% and 98.15%, respectively. The results show that the optimized ISSA-SVM model has a good analog circuit fault diagnosis with an increase in diagnostic accuracy.

Study on adjustable low-frequency sound absorbers based on digital shunt loudspeakers

Low-frequency noise is a critical frequency band that affects people’s physical and mental health. Traditional sound absorption technology is limited in effectiveness at low frequencies due to spatial constraints. Shunt loudspeakers, which consist of a loudspeaker connected to a shunt circuit, have emerged as a rapidly developing solution for low-frequency noise control. However, most shunt circuits are implemented using analog circuits, resulting in poor stability and accuracy due to the presence of parasitic resistance. As a result of this situation, this paper proposes an adjustable low-frequency sound absorber based on digital shunt loudspeakers, where the shunt circuit is realized through digital synthetic impedance based on FPGA technology. Additionally, the acoustic impedance can be easily adjusted by the digital shunt circuit without relying on cavity depth adjustments. Experimental results validate that the proposed sound absorber offers excellent performance in adjustable low-frequency sound absorption, thus confirming its theoretical basis.

Modeling the effect of magnetoelectric nanoparticles on neuronal electrical activity: An analog circuit approach.

This paper introduces a physical neuron model that incorporates magnetoelectric nanoparticles (MENPs) as an essential electrical circuit component to wirelessly control local neural activity. Availability of such a model is important as MENPs, due to their magnetoelectric effect, can wirelessly and noninvasively modulate neural activity, which, in turn, has implications for both finding cures for neurological diseases and creating a wireless noninvasive high-resolution brain-machine interface. When placed on a neuronal membrane, MENPs act as magnetic-field-controlled finite-size electric dipoles that generate local electric fields across the membrane in response to magnetic fields, thus allowing to controllably activate local ion channels and locally initiate an action potential. Herein, the neuronal electrical characteristic description is based on ion channel activation and inhibition mechanisms. A MENP-based memristive Hodgkin-Huxley circuit model is extracted by combining the Hodgkin-Huxley model and an equivalent circuit model for a single MENP. In this model, each MENP becomes an integral part of the neuron, thus enabling wireless local control of the neuron's electric circuit itself. Furthermore, the model is expanded to include multiple MENPs to describe collective effects in neural systems.

Design of Pseudorandom Signal Generator Based on a Dual Memristor Chaotic System

This paper constructs a pseudo-random signal generator based on a dual memristor chaotic system. Firstly, the chaotic characteristics of the dual memristor chaotic system were explored through theoretical analysis and MATLAB numerical simulation, and a MULTISIM simulation circuit for the dual memristor chaotic system was constructed. Then, based on the threshold decision quantization method, a pseudorandom signal generator quantization circuit is formed by connecting an inverter amplifier and a hysteresis comparator on the output side of the analog circuit. Finally, the randomness of the pseudorandom sequence is discussed by NIST test and correlation analysis. The analysis results show that the pseudorandom sequence generated by the pseudo-random signal generator based on the dual memristor chaotic system exhibits good randomness.

Multiple firing patterns, energy conversion and hardware implementation within Hindmarsh-Rose-improved neuron model

The transmission of information between neurons is accomplished in living organisms through synapses. The memristor is an electronic component that simulates the tunability of the strength of biological synaptic connections in artificial neural networks. This article constructs a novel type of locally active memristor and verifies by nonlinear theoretical analysis, locally active analysis and circuit simulation. The designed memristor is simulated as a biological autapse of Hindmarsh-Rose(HR) neuron to obtain the improved HR neuron model of memristive autapse, and the Hamilton energy is obtained according to Helmholtz theorem. By varying the external forcing current and the memristive autapse strength, this article analyses the changes of the Hamilton energy and explores its self-excited and hidden firing behavior. The analog circuit simulation and digital circuit implementation of the HR model confirm the consistency between the mathematical model and the actual behavior, which can advance the field of neuroscience and artificial intelligence.

A Hybrid Scheme for TX I/Q Imbalance Self-Calibration in a Direct-Conversion Transceiver

A generic transmitter (TX) I/Q imbalance self-calibration method, which was designed based on a hybrid analog and digital structure, is proposed in this paper. The whole calibration scheme was implemented using low-complexity digital–analog circuits based on a zero-force feedback loop. In order to eliminate the negative effect of local oscillator (LO) harmonics on the calibration, we used a variable-delay line (VDL) in the analog domain instead of the digital phase compensator. The prototype chip was fabricated within a 0.2∼5.0 GHz direct-conversion transmitter in a 65 nm CMOS process, and measurements found an image rejection ratio (IRR) of 65 dBc.

Extreme multistability of fractional-order hyperchaotic system based on dual memristors and its implementation

In this paper, a fractional-order hyperchaotic system based on dual memristors is proposed by introducing flux-controlled and charge-controlled memristors into a simple RLC circuit. Dynamics of the hyperchaotic system are investigated using bifurcation diagrams, Lyapunov exponents spectrum (LEs), phase diagrams, time-domain diagrams, spectral entropy (SE) and C0 complexity. The results show that it has a plane of equilibria and exhibits rich dynamical characteristics, including hyperchaos, homogeneous and heterogeneous extreme multistability. Meanwhile, the transient transition phenomena as well as the effect of parameters on the complexity and chaotic behavior of the system are also studied. Furthermore, the practical implementation of the system is realized through analog and digital circuit. The experimental results validate the correctness of the theoretical analysis and help to make better use of the hyperchaotic system in applications such as secure communications.

Fault detection in analog electronic circuits using fuzzy inference systems and particle swarm optimization

Fault detection in analog circuits is of great importance to predict the correct operation of the circuit. For this purpose, soft computing techniques such as those based on the application of fuzzy inference systems stand out. However, given the large variability that can exist in analog circuits due to component tolerance, the initial fuzzy inference system (FIS) may not be able to accurately diagnose the different hard faults. This study presents a methodology to diagnose and detect the faults that can occur in analog circuits, which is based on the development of a FIS, starting from a specific fault situation in the analog circuit, and subsequently on the optimization of the membership functions using an evolutionary algorithm so that the adjusted FIS can classify and predict different failure situations. To this end, the application of optimization techniques based on particle swarm optimization (PSO) will be analyzed to develop a FIS capable of predicting different faults. In addition, pattern search algorithm will also be analyzed. A Sallen-Key band-pass filter and a single stage of a small-signal amplifier are used as test circuits. The proposed methodology shows that it is possible to accurately predict the faults that could arise in the circuits under study.

Fully real-time configurable analogue implementation of continuous-time transfer function: Application on fractional controller

This paper proposes a new electronic analog circuit to realize real-time fully configurable continuous-time transfer function. The proposed circuit serves various purposes, including smart controllers, fractional-order controllers, optimal controllers, anti-aliasing filter, and programmable filters. The input signal of the transfer function is continuous and remains continuous throughout the circuit until the output signal is obtained. The proposed approach decomposes the transfer function into elementary first and/or second-order low-pass filters. A new analog first-order low-pass filter circuit is presented, offering advantages over conventional active first-order low-pass filters circuits. These benefits include DC gain and time constant independent of resistor ohmic values, enabling the use of smaller resistors and capacitors for low frequencies, and an expanded frequency working range. Similarly, a new analog circuit for a second-order low-pass filter is proposed, specifically used to obtain complex conjugate poles. The use of digital potentiometers and digital switches controlled by a micro-controller, makes this analog circuit configurable in real-time. As an application, the new circuit is used to realize fractional integrator controller. The circuit gives good similarity between theoretical and experimental measurements.

Investigation of an efficient high cooling-capacity Stirling-type pulse tube refrigerator with passive rod displacer operating at 173 K

Pulse tube refrigerator (PTR) with passive rod displacer is of great potential to realize high-efficiency refrigeration and can be a feasible substitute for the vapor compression system in ultra-low temperature cold storage. However, PTRs with passive rod displacer in that application require high efficiency and substantial cooling capacity, which still need to be developed in previous research. In this paper, a high cooling-capacity PTR with passive rod displacer operating at 173 K was designed, fabricated, and investigated. The special property of acoustic power recovery was exhibited based on an electrical circuit analogy model and energy flow analysis. The structural parameters of PTR with passive rod displacer were optimized by one-dimensional numerical software. The experimental results showed that a cooling capacity of 157.5 W at 173 K was obtained with an input electric power of 500 W. The corresponding relative Carnot efficiency reached 21.8 %. The phase difference between the displacer and piston decreased slightly from 58.1° with the increase of cooling temperature when charging pressure and operating frequency were 2.8 MPa and 65 Hz, respectively. The phase difference was determined by the operating frequency and was slightly affected by charging pressure, cooling temperature, and input electric power. Based on the validated numerical models, PTR with passive rod displacer and inertance-tube-type PTR were compared. The numerical results showed that both enthalpy and PV power enlarged at the T-junction in the PTR with passive rod displacer due to acoustic power recovery. According to the acoustic-mechanical–electrical coupling phasor diagram, the phase difference between pressure and piston displacement decreased because of the mass flow superposition at the T-junction, affecting the output capability of the linear compressor. The efficient high cooling-capacity prototype verifies that PTR with passive rod displacer has a bright future in ultra-low temperature engineering applications.

Design and Comparison of Constant Transconductance Architectures

Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.