Analog Circuit Design Research Articles

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 μm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

A Novel Dung Beetle Optimization Approach for Automatic CMOS Analog Circuit Design

The main objective of the automated circuit sizing technique is to deal with the challenges of design tradeoffs in analog circuit design with improved accuracy and efficacy. Analog circuit design represents a multi-objective optimization challenge, where designers must properly balance various performance factors such as input and output impedance, power dissipation, area, unity-gain bandwidth, slew rate, and open-loop DC gain. Traditional design equations provide a sizing of differential amplifier MOS transistors, further optimization can be achieved through the application of meta-heuristic search techniques. Meta-heuristic search techniques can be used as local optimizers in a smaller search area to improve the optimization of design parameters. The differential amplifier circuit with current mirror load is optimized through the application of the Dung Beetle Optimization (DBO) algorithm. By using an evolutionary algorithm called DBO, all the required parameters were achieved with the least amount of transistor area and power dissipation when compared to the results of the Seeker Optimization Algorithm (SOA), Opposition based Harmony Search Algorithm (OHS), craziness-based particle swarm optimization (CRPSO), and Cuckoo Search (CS) algorithms.

Design and Application of Programmable Analog Circuit for Solving Lyapunov Matrix Equation Based on Memristors

Design and Application of Programmable Analog Circuit for Solving Lyapunov Matrix Equation Based on Memristors

PMOS Integrated Current Mirror for Biomedical Applications

Abstract: This paper presents the design and implementation of a PMOS integrated current mirror tailored for biomedical applications. Current mirrors are fundamental building blocks in analog circuit design, finding extensive use in various signal processing stages, including amplification, filtering, and signal conditioning, critical in biomedical instrumentation. The proposed PMOS current mirror offers several advantages suited for biomedical applications, such as low power consumption, high input impedance, and compatibility with standard CMOS processes, ensuring seamless integration with other circuitry on a chip. The design focuses on achieving high accuracy and stability to facilitate precise measurement and processing of biomedical signals, essential for applications like biosensing, medical imaging, and neural interfacing. Simulation results demonstrate the efficacy of the proposed PMOS current mirror in meeting the stringent performance requirements of biomedical devices while offering robustness against process variations and environmental noise. This work contributes to advancing the state-of-the-art in integrated circuit design for biomedical applications, promising enhanced reliability and efficiency in nextgeneration healthcare technologies.

Novel GA‐OCEAN Framework for Automatically Designing the Charge‐Pump Circuit

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Effect of Filters in Photoplethysmography Analog Signals Using Open-Source LTspice Software

Analog signal processing plays a crucial role in the realm of biomedical signal analysis. This study investigates the application of analog signal processing techniques in the domain of biomedical signals, focusing on enhancing the quality and reliability of recorded physiological data. The primary emphasis is on the implementation of analog filters and amplifiers to address challenges such as noise reduction, signal conditioning, and overall signal improvement. The processing of physiological signals, such as photoplethysmography (PPG), necessitates the use of amplifiers and filters within a range of 0.4 to 5Hz. Signal noise can stem from various sources, including the test subject’s muscle movement, respiration, humming, power line interference, or even from the device itself. The research methodology involves a comparison of 3 different order of Butterworth filter circuits and their impact on the signal. The test input signal is derived from an SpO$_2$ simulator, read by a standard PPG sensor, and processed by the internal 12-bit ADC of Nucleo-F429ZI. The resulting data is stored in CSV format for subsequent use in filter design simulations with SPICE. For analog circuit designers, the utilization of SPICE in the form of LTspice proves invaluable. This open software, LTspice, boasts a simple yet powerful interface, facilitating a focus on the conceptualization and performance of the design

2D BDiode – A switchable bidirectional diode for analog electronic circuits fabricated entirely from 2D materials

The advent of two-dimensional (2D) materials has led to innovative and compact electronic devices with remarkable properties. In this work, we introduce a switchable bidirectional diode (2D BDiode), fabricated entirely using different 2D materials, that serves as a fundamental building block for various analog circuit applications. This proof-of-concept diode exhibits the ability to control the flow of current in both forward and reverse bias configurations, enabling advanced functionality in the realm of analog circuit design. We provide a SPICE-based model for the diode based on current-voltage device characterization, capturing its behavior under different biasing conditions, and finally demonstrate a few potential use cases of the 2D BDiode including AC/DC conversion, DC/AC conversion and charge pump circuits.

Artificial intelligence in analogue circuit design

Analog circuit design plays an integral part in modern society; however, traditional approaches often fall short in terms of efficiency and effectiveness. This paper explores the application and challenges presented by artificial intelligence (AI) technologies in analog circuit design. The objective of this paper was to evaluate the capacity of artificial intelligence technologies such as machine learning, deep learning and reinforcement learning to advance circuit modeling, optimization and layout design processes. A comprehensive literature review and analysis were performed. The study finds that while AI can make significant contributions to circuit design, several challenges must first be overcome. These include data scarcity for training AI models and the opaque nature of AI decisions which prevent their widespread acceptance. Finally, future research directions such as creating synthetic data or developing more interpretable AI models were identified as potential future research avenues.

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications.

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Abstract: Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

Pareto Optimization of Analog Circuits Using Reinforcement Learning

Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require the designer to optimize for multiple competing objectives, which poses a crucial challenge. Motivated by these practical aspects, we propose a novel method to tackle multi-objective optimization for analog circuit design in continuous action spaces. In particular, we propose to (i) extrapolate current techniques in Multi-Objective Reinforcement Learning to continuous state and action spaces and (ii) provide for a dynamically tunable trained model to query user defined preferences in multi-objective optimization in the analog circuit design context.

Design and implementation of a preset operational amplifier based on basic digital and analog hybrid circuit

In the vast landscape of electronic engineering, the indispensable roles of both analog and digital circuits are unequivocally recognized. Analog circuits, with their foundational principles, are extensively harnessed in areas encompassing audio, video, power systems, and particularly, amplifiers. Conversely, digital circuits, integral to modern-day technological advancements, are dominantly present in computing platforms, telecommunication systems, control mechanisms, and data storage infrastructures. Amplifiers, a cornerstone in analog circuit designs, principally focus on magnifying the amplitude of input signals, whether it be in terms of voltage or current. This amplification process hinges on the strategic configuration of electronic elements such as transistors, resistors, and capacitors. This paper endeavors to marry the attributes of digital and analog circuits. Through the adept utilization of fundamental electronic components, an innovative amplifier design capable of preset amplification ratios is birthed. The practicality and efficacy of this amplifier are rigorously validated via its hands-on assembly and experimental testing in a laboratory setting. Results consistently underscore the amplifiers adeptness in delivering precise signal amplification, conforming to its predetermined ratios. Such a design, rooted in its simplicity yet offering profound versatility, beckons further exploration. It stands as a beacon for potential future adaptions, tailored to suit a gamut of applications, and is poised to seamlessly dovetail into more sophisticated circuit systems.

BAG2-assisted analog layout synthesis for TSMC 65 nm and GPDK 45 nm

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continuing to be developed and targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley Analog Generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow and it encourages design reuse due to using parameterized generators which can be scaled as required. This reduces the layout development time compared to manual handmade layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65 nm and Cadence GPDK 45 nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

Incremental reinforcement learning for multi-objective analog circuit design acceleration

The design of high-performance analog circuits is a time-consuming process that requires the involvement of highly qualified designers and frequent tedious interactions with circuit simulators. This sets a need for a method that accelerates the circuit design process and reduces unnecessary designer-simulator interactions. Existing methods are either slow or unable to deal with complex tasks. This paper proposes a simulation-based optimization method based on a deep reinforcement learning (DRL) agent to optimize analog circuits and accelerate the design process. In this method, the DRL agent exploits the soft-actor-critic algorithm based on an improved reward function considering multiple conditions to expedite the parameters optimization step of analog circuits. The designer provides the RL agent with the circuit testbench, design requirements and circuit parameters. The agent then repetitively interacts with the circuit simulator to tune these parameters. In this work, an incremental RL approach is also proposed to deal with complex circuits. Incrementality is found to be increasingly beneficial as the circuit complexity increases (increased number of design parameters and competing objectives). The effectiveness of the proposed method was validated on a complex circuit defined by a design space comprising as many as 36 dimensions (17 design variables and 19 competing objectives). The reported results demonstrate that our method can significantly accelerate the design process and yield high-performance optimized designs. Notably, the required number of simulation steps is on the order of 1e3, which is one to two orders of magnitude more efficient than similar state-of-the-art DRL approaches.

Chaos and Synchronization - Potential Ingredients of Innovation in Analog Circuit Design?

Chaos and Synchronization - Potential Ingredients of Innovation in Analog Circuit Design?

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology

Topology optimization of analog circuit design via global optimization using factorization machines with digital annealer

Topology optimization of analog circuit design via global optimization using factorization machines with digital annealer

Parsing Netlists of Integrated Circuits from Images via Graph Attention Network.

A massive number of paper documents that include important information such as circuit schematics can be converted into digital documents by optical sensors like scanners or digital cameras. However, extracting the netlists of analog circuits from digital documents is an exceptionally challenging task. This process aids enterprises in digitizing paper-based circuit diagrams, enabling the reuse of analog circuit designs and the automatic generation of datasets required for intelligent design models in this domain. This paper introduces a bottom-up graph encoding model aimed at automatically parsing the circuit topology of analog integrated circuits from images. The model comprises an improved electronic component detection network based on the Swin Transformer, an algorithm for component port localization, and a graph encoding model. The objective of the detection network is to accurately identify component positions and types, followed by automatic dataset generation through port localization, and finally, utilizing the graph encoding model to predict potential connections between circuit components. To validate the model's performance, we annotated an electronic component detection dataset and a circuit diagram dataset, comprising 1200 and 3552 training samples, respectively. Detailed experimentation results demonstrate the superiority of our proposed enhanced algorithm over comparative algorithms across custom and public datasets. Furthermore, our proposed port localization algorithm significantly accelerates the annotation speed of circuit diagram datasets.

Intelligent Optimization of CMOS Operational Amplifier Using 3D Ant Colony Optimization

This paper presents the use of an artificial intelligence (AI) tool based on ant colony behavior to design an operational amplifier circuit. The ant colony optimization (ACO) is implemented in a hybrid evolutionary sizing method to automate analog circuit design. This new meta-heuristic approach that combines the artificial intelligence of an ant colony and the 3D matrix method is developed to determine the optimal dimensions and the main influencing performances of fundamental analog circuits and, including operational amplifiers (op-amps). The proposed methodology uses ACO and Cadence Spectre as dimensioning techniques and implementation platform, respectively. The Three Dimensions (3D) ACO algorithm is successfully used for analog circuit sizing, and the obtained results demonstrate its effectiveness in sizing basic and more complicated analog circuits.

The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology

The complexity of digital circuits is constantly rising. Analog computing can be an excellent alternative to overcome the complexity issue. Operational Amplifiers play a serious role in many analog circuit designs. This paper presents a new implementation approach to an analog subtractor. This design enjoys high speed and low power dissipation using Carbon Nanotube FETs (CNTFETs). We have also achieved a significant improvement in terms of the number of transistors and chip area. The proposed design considerably decreases power consumption and optimizes the chip area. The same performance can be achieved when designing a high-quality Differentiator. It is to remark that there is no need to use a huge number of resistors and capacitors. In this design, no additional voltage or current sources have been used. HSPICE and the Stanford 32 nm CNTFET model are used to simulate the proposed circuit. The comparisons with State-of-the-art prove the performance of this design.