Analog Blocks Research Articles

A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom processing engine with data path, memory architecture and instruction set optimized for efficient execution of compute intensive test and calibration algorithms. The innovative BIST engine is complemented with a calibration and test sequencing methodology exploiting the embedded test hardware, to dynamically correct for transceiver imbalances and non-idealities, as well as to estimate performance parameters such as Error Vector Magnitude (EVM). The engine has been integrated with a WiFi transceiver in a 32 nm SoC test chip to demonstrate the functionality of this framework. This implementation covers an area of 0.63 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and provides similar performance (e.g., improvements up to 10 dB in EVM for Rx IQ imbalance compensation) to off-chip testing without relying on expensive equipment.

High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate

This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Stability on single devices and on an elementary complementary digital circuit (ring oscillator) is studied, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices. These devices are used to manufacture several analog and digital building blocks. The design is carried out using a model specifically developed for this technology, and taking into account the parametric variability. High-frequency measurements of printed envelope detectors show improved speed performance, resulting from the high mobility of the OTFTs. In addition, a compact dynamic flip–flop and a low-offset comparator are demonstrated, thanks to availability of both n-type and p-type OTFTs in the technology. Measurement results are in good agreement with the simulations. The circuits presented establish a complete library of building blocks for the realization of a printed RFID tag.

Mismatch Characterization and Calibration for Accurate and Automated Analog Design

Device mismatch has long prevented the implementation of accurate high density analog computation. This paper presents the Reconfigurable Analog Signal Processor (RASP) 2.9a, a 350 nm double-poly CMOS chip designed for the implementation of accurate analog computation. The chip is the densest field programmable analog array (FPAA) to date, containing over 130 k programmable floating gate switch elements (SWEs). The paper reviews an algorithm for rapidly programming the charge on floating gate switch elements with 10.2 bit accuracy. An automated algorithm based on the EKV transistor model is developed to rapidly characterize device mismatch, the Early effect, capacitive drain coupling, and temperature dependent behavior. This paper empirically verifies the characterization, using the precise floating gate programming methods to offset the errors and create current sources with 2.2% RMS error over a dynamic range of 25 dB. The current sources are then modified to create current mirrors and vector-matrix multipliers, accurate for currents down to 8 nA. Together with the computational analog blocks, these linear circuits can be synthesized into a wide range of extremely low power linear and nonlinear functions. The calibration routine, in combination with preexisting design tools, allows the automated synthesis, placement, and accurate programming of large classes of circuits on an FPAA.

MODEL OF DIGITAL FIBER-OPTIC SYSTEM FOR MEASURING OBJECT SIZES

In this study a new approach to get a generalized mathematical model of digital fiber-distributed interferometer measuring system has been proposed. By using this approach generalized equations of conversion for digital fiber-optic converters of measured object’s geometrical coordinates have been obtained, joining all private mathematical models of information processes which occur in analogue, analogue-digital and digital structural blocks while working under static and dynamic conditions. In general, the essence of the proposed approach is based on representation of characteristics of the "coordinate point- code" presented in the form of the equation of an ideal digital-to-analog conversion of the source code, the processes of bit code change given in the form of logical functions of input points and movement of actual multi-dimensional parameter measuring path.

Implementation Analog Neural Network for Electronic Nose using Field Programable Analog Arrays (FPAA)

Electronic nose is a device detecting odors which is designed to resemble the ability of the human nose, usually applied to the robot. The process of identification of the electronic nose will run into a problem when the gas which is detected has the same chemical element. Misidentification due to the similarity of chemical properties of gases is possible; it can be solved using neural network algorithms. The attendance of Field Programmable Analog Array (FPAA) enables the design and implementation of an analog neural network, while the advantage of analog neural network which is an input signal from the sensor can be processed directly by the FPAA without having to be converted into a digital signal. Direct analog signal process can reduce errors due to conversion and speed up the computing process. The small size and low power usage of FPAA are very suitable when it is used for the implementation of the electronic nose that will be applied to the robot. From this study, it was shown that the implementation of analog neural network in FPAA can support the performance of electronic nose in terms of flexibility (resource component required), speed, and power consumption. To build an analog neural network with three input nodes and two output nodes only need two pieces of Configurable Analog Block (CAB), of the four provided by the FPAA. Analog neural network construction has a speed of the process 0.375 μs, and requires only 59 ± 18mW resources. DOI: http://dx.doi.org/10.11591/ijece.v2i6.1501

Design and implementation of an ultra-low power passive UHF RFID tag

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm2. Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of −12 dBm.

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm2 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.

Design of Low Power Sigma Delta ADC

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

Circuit-level Design of a Power Supply Unit with Extra Low-noise Output for Portable Integrated SoCs

Switch-mode voltage regulators are considered as the dominant choice for low-power integrated power supplies. Employing the advantages of a switch-mode voltage regulator in 0.18µm CMOS technology, a power supply has been designed for a complete System-on-Chip (SoC). While offering enough drive capability for the entire system, the supply provides an extra highly-regulated output for noisesensitive analog blocks. At first, a front-end buck regulator converts the time-variant unregulated input voltage to an initially-regulated general voltage. To further regulate this voltage for noise-sensitive blocks, a new continuous-time buffered voltage source has been added to the circuit. To maximize power efficiency and to benefit from an initiallyregulated input, this source is connected to the front-end switch-mode regulator output. For proper operation, the minimum input voltage to the supply is 1.3V. With this minimum input voltage, the 1.1V switching regulator sources up to 1A output current. The continuous-time 0.9V- buffered source provides up to 100mA for noise-sensitive units. It converts the 1.1V regulated voltage to a 0.9V smooth output.

A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm$^{2}$ and 500 mW in 40 nm Digital CMOS

A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiplying digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of -0.5/+0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm2 in 40 nm CMOS process.

Nucleos(t)ides analog block HBV mother-to-child transmission in pregnancy HBV carriers-agreement and challenges

目前,我国由于新生儿普遍接种乙型肝炎疫苗后人群总的HBsAg携带率已经降至7.18％,但20岁以上的成年人中,HBsAg的平均携带率仍高达10％左右,在这些人群中有相当一部分是育龄期妇女.因此,HBV的母婴垂直传播仍然是一个十分严重的公共卫生问题,且母婴传播感染新生儿或婴幼儿后,超过80％的人将成为慢性HBV感染者.那么如何阻断和降低HBV母婴垂直传播一直是我们面临的严重挑战. 关键词：肝炎病毒;乙型;传播;母婴;阻断;核苷(酸)类似物

A Translinear, Log-Domain FPAA on Standard CMOS Technology

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 × 5 RTC FPAA testchip was implemented in 0.35- μm CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 μW/TE and precision errors below 3%.

Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks

SystemC-AMS allows the modeling of complex heterogeneous systems at different levels of abstraction using different modeling styles, called Models of Computation (MoC). This work presents an approach for including energy consumption information in high-level modeling of linear electrical circuits described using the SystemC-AMS Linear Signal Flow (LSF) MoC. The method introduced here proposes to start from a description of the system at a low level of abstraction, which is a description using the SystemC-AMS Electrical Linear Network (ELN) MoC or a SPICE netlist. The following steps of the proposed approach automatically extract the state space model corresponding to the analyzed circuit. During the state equation extraction, the supply current signal is regarded as an output of the state space model. This output allows an instantaneous monitoring of the power consumption of the system at the LSF description level. The case study that we present as a proof of the proposed approach is a passive fourth-order low pass filter. Then, we present a possible application: a power consumption comparison between two circuits having the same transfer function.

LOW VOLTAGE CURRENT CONVEYOR-BASED FIELD PROGRAMMABLE ANALOG ARRAY

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1 V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of ±0.5 V.

Fault-tolerant A/D converter using analogue voting

Analogue and digital circuits are both prone to failure because of device degradations, transient upsets and large parametric variations. Redundancy techniques, such as N-tuple modular redundancy, have been widely used to correct faulty behaviour of components and achieve high reliability for digital circuits. In this study, the authors propose a redundancy based fault-tolerant methodology for analogue circuits. In particular, the authors focus on highly reliable analogue-to-digital converter, which is a critical component in many mixed-signal systems. The authors methodology employs redundant analogue blocks and chooses the best result using an innovative analogue voter. Simulation results are reported to verify the concepts, measure the system&apos;s reliability and trade off reliability against cost and power.

Hardware Design of Diameter Analyzing System for Liquid and Gas Pipeline

MFL_PIG (Magnetic Flux Leakage detector) is the most widely used long-range pipeline inspection equipment to detect corrosion condition of the pipeline and thus to avoid serious pipeline accidents. In order to collect the diameter information of the pipeline, geometry pig (also called diameter analyzing system) is used before applying the MFL_PIG. In this paper, the hardware design of a new modern smart diameter analyzing system which is suitable for detecting cracks and corrosions in the pipeline with different diameters is introduced. Miles round system,as one of important part of the system, is investigated in detail. A pulse optimum algorithm for miles round system is put forward and its principle and realization method is discussed. Reverse time algorithm is adopted in miles round system to solve the problem of location precision. In the end, one of the verification tests is given to measure reliability of the system and results showed that the optimum algorithm works well when frequency of the analog block wave is in the range of 100Hz to 1MHz.

Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions

This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The methodology is based on small-signal analyses performed at the individual analog and digital microcontroller building block level, on electromagnetic simulations carried out to describe the power supply network at the chip- and at the package-level and on the analysis of the chip layout and process technology data to model the parasitic coupling paths through the semiconductor substrate. The electrical model of microcontrollers generated according to this methodology, consists of a low-complex and linear netlist that provides insight regarding the relationships between the design parameters and noise propagation paths in the early design phases, through simulations in a SPICE-like environment. The proposed approach does not rely on experimental test results. In this paper, the electric model of an 8 bit microcontroller, which validity has been proved by scattering parameter and conducted emission measurements, is derived.

A New Universal Second-Order Filter using Configurable Analog Building Blocks (CABs) for Filed-Programmable Analogue Arrays

In this paper, the design of a universal second-order filter using configurable analog blocks (CABs) for field programmable analog arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by digitally modifying the block's biasing conditions. Using at most four CABs, this article shows that it is possible to design a versatile second-order filter realizing all the standard five filter functions; lowpass, highpass, bandpass, notch and allpass. SPICE simulation results using practical bipolar junction transistor (BJT) parameters confirm the feasibility of using the CABs in designing second-order filters.

An Asynchronous Spike Event Coding Scheme for Programmable Analog Arrays

This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-μm CMOS technology are presented.