A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

Abstract

This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom processing engine with data path, memory architecture and instruction set optimized for efficient execution of compute intensive test and calibration algorithms. The innovative BIST engine is complemented with a calibration and test sequencing methodology exploiting the embedded test hardware, to dynamically correct for transceiver imbalances and non-idealities, as well as to estimate performance parameters such as Error Vector Magnitude (EVM). The engine has been integrated with a WiFi transceiver in a 32 nm SoC test chip to demonstrate the functionality of this framework. This implementation covers an area of 0.63 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and provides similar performance (e.g., improvements up to 10 dB in EVM for Rx IQ imbalance compensation) to off-chip testing without relying on expensive equipment.