Analog Behavioral Modeling Research Articles

Threshold Inverter Quantizer-Based 2-Bit Comparator using Spatial Wavefunction Switched (SWS) FET Inverters: Power Dissipation Analysis

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [1, 2, 4, 5]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [1-3, 5, 6]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [1,3,4,9]. The transient behavior of the inverter circuit is evaluated using 180 nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations.

Behavioral Modeling Method of Macromodels for Interconnected Systems With Frequency Characteristics and Nonlinear Termination Networks

This study presents a behavioral macromodeling method for electronic or electrical interconnected systems, when there are frequency-characterized interconnects loaded by nonlinear terminations in systems. Analog behavioral modeling (ABM) was leveraged to capture frequency-dependent characteristics of multiconductor interconnects and properties of nonlinear terminations. Black-box macromodels were developed from the external mathematical behavior of parts, and real systems could be simulated in the SPICE circuit solver. Also, several critical points and constraints concerning ABM models were analyzed and proposed.From the validation results, the relative errors of proposed models are all less than 3%, and the execution time reduces by a factor over 10 concerning the existing interconnect model, which implies the proposed interconnect model can significantly improve the simulation efficiency, and the analysis accuracy can be guaranteed using proposed models of interconnect systems.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

A Rule-Based Approach for Grey Hole Attack Prediction in Wireless Sensor Networks

The Wireless Sensor Networks (WSN) are vulnerable to assaults due to the fact that the devices connected to them have a reliable connection to the internet. A malicious node acts as the controller and uses a grey hole attack to get the data from all of the other nodes in the network. Additionally, the nodes are discarding and modifying the data packets according to the requirements of the system. The assault modifies the fundamental concept of the WSNs, which is that different devices should communicate with one another. In the proposed system, there is a fuzzy idea offered for the purpose of preventing the grey hole attack from making effective communication among the WSN devices. The currently available model is unable to recognise the myriad of different kinds of attacks. The fuzzy engine identified suspicious actions by utilising the rules that were generated to make a prediction about the malicious node that would halt the process. Experiments conducted using simulation are used to determine delay, accuracy, energy consumption, throughput, and the ratio of packets successfully delivered. It stands in contrast to the model that was suggested, as well as the methodologies that are currently being used, and analogue behavioural modelling. In comparison to the existing method, the proposed model achieves an accuracy rate of 45 percent, a packet delivery ratio of 79 percent, and a reduction in energy usage of around 35.6 percent. These results from the simulation demonstrate that the fuzzy grey detection technique that was presented has the potential to increase the network’s capability of detecting grey hole assaults.

Power Dissipation and Cell Area: Quaternary Logic CMOS Inverter vs. Four-State SWS-FET Inverter

Power dissipation of spatial wave function switched (SWS) FETs four-state inverter is the focus of this paper. The current can flow through multiple channels in a (SWS)-FETs, which comprises vertically stacked quantum well/quantum dot channels. Using four voltage levels, the four-state SWS transistor inverter circuit is simulated. Cadence was used to perform SWS-FET inverter circuit simulations to evaluate power dissipation. To develop the SWS-FET model, an Analog Behavioral Model (ABM) and the Berkeley Short-Channel IGFET Model (BSIM4.6) were combined. To evaluate the inverter circuit’s transient behavior, a 0.18-μm technology node was used. The improvement in power dissipation, the frequency of operation, and reduction in cell area are all approximately is by a factor of 2-3. As a result, circuits based on SWS-FET inverters overcome the limitations of earlier implementations of 4-state logic circuits.

Propagation Delay Evaluation for Spatial Wavefunction Switched (SWS) FET-Based Inverter

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

Development of Electrothermal Models for Electrical Traction

In this paper, improved electrothermal models of the power diode and IGBT have been developed. The main local physical effects have been considered. The proposed models are able to deal with electrical and thermal effects. The models were confirmed by comparison with other models having similar characteristics for different circuits and different temperatures. The developed models are implemented in a traction unit to study the electrothermal performance in an electric vehicle system. The models were implemented in the Pspice circuit simulation platform using standard Pspice components and analog behavior modeling (ABM) blocks. The switching performance of the diode and the IGBT have been studied under the influence of different circuit elements in order to study and estimate the on-state and switching losses pre-required for the design of various topologies of converters and inverters. The comparison shows that these models are simple, configurable with the electrical circuit simulator software. They are better able to predict the main circuit parameters needed for power electronics design. Transient thermal responses have been demonstrated for single pulse and repetition modes. The obtained results show that our model is suitable for a fully electrothermal use of power electronic circuit simulations.

An Improved Memristor Model Based on the Electrochemical Metallization Effect as a Synapse for Biomimetic Applications

Herein, an improved memristor model with a controllable forgetting rate due to ion diffusion is proposed. A synaptic learning circuit based on this model is simulated with PSpice to complete synaptic bionics. First, the pulse pair superposition method, which is consistent with biological phenomena, is used to verify spike timing‐dependent plasticity (STDP); this proves that the modified model simulates biological synaptic behavior. Second, a habituation circuit constructed from a memristor and an analog behavioral modeling (ABM) device is designed to realize nonassociative learning. Finally, a new circuit with the improved model is built for Pavlov's associative memory implementation, simplifying the complexity of the circuit. The improved model can better realize the basic learning and memory modes of organisms and thus provide more brain‐inspired computing options.

Modeling and Simulation of Monolithic Single-Supply Power Operational Amplifiers

In this paper a simple PSpice (Personal Simulation Program with Integrated Circuit Emphasis) macro-model was developed, and verified for monolithic power operational amplifiers operated with a single-supply voltage. The proposed macro-model is developed using simplification and build-up techniques for macro-modeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macro-model also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model is implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit is built using standard PSpice components and analog behavioral modeling blocks. The accuracy of the model is verified by extracting the model parameters for single-supply power operational amplifier TDA2005 from ST Microelectronics as example. The effectiveness of the model is validated by comparing the simulation results of the electrical parameters with the corresponding measured values obtained by experimental testing of sample circuits. The comparative analysis shows that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.

Electrothermal Modeling of the Insulated Gate Bipolar Transistor (IGBT) Using PSpice: Application to DC–DC Converter

In this paper, an improved electrothermal model of power IGBT was developed. The main local physical effects were taken into consideration. The suggested model is able to address the electrical and thermal effects. The model was confirmed through a comparison with other models having close characteristics for different circuits (DC–DC converter, turn-on and turn-off) and different temperatures. The IGBT model was implemented in the PSpice circuit simulation platform using PSpice standard components and analog behavior modeling (ABM) blocks. The IGBT switching performance was investigated under influence of different circuit elements (such as stray inductance, gate resistance and temperature) in order to study and estimate the on-state and switching losses pre-requisite for the design of various converter and inverter topologies. The comparison shows that these models are simple, tunable with the electric circuit software simulator. They are more capable of predicting the main circuit parameters needed for power electronic design. The transient thermal responses were demonstrated for the single pulse and repeat modes. The achieved results show that our model is suitable for full electrothermal simulations of power electronic circuits.

Fast Validation of Mixed-Signal SoCs

Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10, $000\times $ speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5, $000\times $ speedup using synthesizable analog models in FPGA emulation.

A Spice-Compatible Macromodel for Field Coupling to Underground Transmission Lines Based on the Analog Behavioral Modeling

A Spice-Compatible Macromodel for Field Coupling to Underground Transmission Lines Based on the Analog Behavioral Modeling

3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance gm and channel conductance gD using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).

Recognition of grey hole attacks in wireless sensor networks using fuzzy logic in IoT

AbstractSince the devices in Internet of Things (IoT) are always interconnected with a stable Internet connection, they are prone to attacks. In the grey hole attack, a malicious node acts as a central controller to obtain data from all the nodes and it drops and alters the data packets as per its wish. In this way, the grey hole attack alters the core concept of the IoT, which enables different devices to communicate with each other. To prevent the grey hole attack and enable efficient communication between the IoT devices, a fuzzy concept is introduced in this article. Previous methods have not proficient in spotting uncountable kinds of grey hole attacks. The fuzzy engine identifies the suspicious activity that takes place in the network by the rules generated and identifies the malicious node and stops its function immediately. The simulation experimentation is carried out for accuracy, delay, energy consumption, packet delivery ratio and throughput, and the simulation contrasts with the proposed algorithm, analog behavioral modeling (ABM), and other previous techniques. The proposed system provides an accuracy rate of 45%, a packet delivery ratio of 78%, and reduced energy consumption of 35.6% compared to the previous ABM approach. Simulation outputs showed that the proposed fuzzy grey detection technique is a proficient scheme for detecting grey hole attacks and improving network capability.