Amplifier Topology Research Articles

Enhanced phase sensitivity in a feedback-assisted interferometer

The topology of feedback optical parametric amplifier (FOPA) renders a number of significant advantages over the topology of traditional optical parametric amplifier (TOPA) such as a higher degree of quantum correlation, all-phase entanglement enhancement, and the robustness of the losses. Here, we propose a feedback-assisted interferometer based on the topology of FOPA for quantum metrology. We theoretically study the phase sensitivity with the method of homodyne detection and product detection. By manipulating the feedback strength of the FOPA, the phase sensitivity can be further enhanced, and approach the quantum Cramér-Rao bound. Furthermore, we demonstrate that our proposal is superior to the SU(1,1) interferometer based on the topology of TOPA.

Exploring Transimpedance Amplifier Topologies: Design Considerations and Trade-Offs

Exploring Transimpedance Amplifier Topologies: Design Considerations and Trade-Offs

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (Psat) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (Pavg) and 47–53% average drain efficiency (DEavg). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD).

Design and Development of GaN-Based Power Amplifier for Radar Applications

This paper presents a comprehensive overview of Gallium nitride (GaN)-based power amplifier (PA) design for various frequency bands. GaN-based technology has emerged as a promising alternative to traditional silicon-based amplifiers due to its superior performance characteristics, which are discussed in this paper. This paper also discusses the key design parameters and challenges associated with PA design. Various design techniques and topologies for GaN power amplifiers are explored besides addressing theoretical considerations of PA design along with a complete systematic design procedure for L-Band amplifier using the wolfspeed large signal GaN HEMT model. To further demonstrate the useful methodology, the designs of S-band and C-band PAs are also presented. GaN-based devices are very promising candidates for high-power applications. It is widely used in various high-power applications including communication and radar.

A 6-/12-dB back-off reconfigurable Doherty-like load modulated balanced amplifier with compact area and wide bandwidth

This article presents a Doherty-like Reconfigurable Load Modulated Power Amplifier (R-LMBA) topology, which enables a broadband 6-/12-dB power back-off (PBO) reconfiguration by rearranging the bias voltages of the sub-amplifiers with compact area. The proposed R-LMBA guarantees proper phase differences among the three sub-PAs across the entire operating frequency band without the need for a bulky phase shifter that is adopted in conventional LMBAs. The design equations for the R-LMBA are proposed and analyzed in detail. A proof-of-concept PA has been designed in 0.1 μm GaAs pHEMT process to verify the proposed concept. In Mode-1, from 30 to 40 GHz, it achieves saturated output power (Psat) of 27.7–29.1 dBm with peak power added efficiency (PAE) of 28.5–34.4%, and 16.8–22.1% PAE at 6-dB PBO with its best 1.29 × efficiency enhancement over a Class-B counterpart. In Mode-2, it exhibits 28 dBm Psat with 30% peak PAE, and a PAE of 25%/13.6% at 6-/12-dB PBO, which is 1.67 × /1.81 × over an ideal Class-B PA. Besides, in Mode-1/-2, the PA demonstrates 21.3/20.3 dBm average output power (Pavg) and 17.9%/22.1% average PAE (PAEavg) with −28.1/-23.8 dB error vector magnitude (EVM) and −29.1/-25.9 dBc adjacent channel leakage ratio (ACLR) under 6-Gb/s 64-QAM modulated signal at 35 GHz.

A Defects Classification Algorithm for the Hybrid OBT–IDDQ Fault Diagnosis Technique in Analog CMOS Integrated Circuits

In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current ([Formula: see text]). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output, operational amplifier (opamp) topology. The filter is custom designed targeting the 180-nm CMOS technology. Hundreds of time-domain simulations and analyses of the circuit output signal are performed in order to obtain the fault dictionary. The presented results show that the proposed hybrid OBT–IDDQ methodology is significantly more efficient in the defects coverage than any of the particular test methodologies alone. Subsequently, the specific algorithm for the defects classification is proposed. Based on the classification, certain degree of diagnosis of the individual defect, or a group of defects, can be achieved.

A hybrid amplifier topology for low‐noise direct‐coupled front ends

SummaryHybrid amplifiers combine discrete transistors with operational amplifiers (OAs) achieving superior characteristics compared with commercially available OAs, while keeping simple structures and a reduced number of parts. A single‐ended amplifier topology based on a junction field‐effect transistor (JFET) is proposed as a means of achieving very low input noise levels, both in current and voltage. It is direct‐coupled and allows to place a high‐pass filter at its input to preserve input range, or at its output to optimize noise. The proposed topology results in a low input capacitance and low input‐current noise, making it suitable for applications where multiple amplifiers are connected in parallel to achieve ultra‐low noise levels. The amplifier's gain is set by a resistor ratio, being suitable for instrumentation front ends. The circuit analysis and design equations are provided to adapt it for different applications and, as an example, an amplifier with a gain of 40 dB and a bandwidth from DC to 1 MHz was designed, built, and tested. The dominant noise contribution of the amplifier was the JFET (a JFE2140 device), featuring an input noise voltage of , that is reduced to when two amplifiers are connected in parallel.

Exploring Transimpedance Amplifier Topologies: Design Considerations and Trade-offs

Exploring Transimpedance Amplifier Topologies: Design Considerations and Trade-offs

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

Comparison of single event effect on cascoded low noise amplifier performance metrics for two different frequencies

This manuscript examines the impact of single event effects (SEEs) on the well-known cascoded low noise amplifier (LNA) topology connected with an inter-stage inductor sandwiched between the common source (CS) and common gate transistors for boosting the LNA parameters (i.e., gain, etc). In this article, we have considered that the LNA operates at two different frequencies, such as 10 and 30 GHz, in a radiation-prone environment. The effect of SEEs is analyzed in two ways: (i) non-applying a RF input with dc voltage only, and (ii) applying a RF input with dc bias voltage. The first analysis uses basic integration to evaluate the collected charge (QCollected) for a drain terminal momentary current spike with a suitable time period, and the second analysis estimates the LNA output discontinuity (distortion) using a spectrogram (short-time FFT) to determine the radiation strikes on the cascoded LNA. The collected charge is calculated in the temporal analysis, and the discontinuity of LNA’s RF output is analysed using the spectrogram in the frequency domain analysis. From the temporal and frequency analysis, the LNA that operates at a lower frequency (10 GHz) provides more discontinuity in LNA output (causing more disturbance) than the LNA that operates at a higher frequency (30 GHz).

Ka-band stacked and pseudo-differential orthogonal load-modulated balanced power amplifier in 22 nm CMOS FDSOI

Abstract This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ( $P_{\rm 1\,dB}$ ). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (Pavg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm Pavg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency.

Performance evaluation of evolutionary algorithms for analog integrated circuit design optimisation

An automated sizing approach for analog circuits using evolutionary algorithms is presented in this paper. A targeted search of the search space has been implemented using a particle generation function and a repair-bounds function that has resulted in faster convergence to the optimal solution. The algorithms are tuned and modified to converge to a better optimal solution with less standard deviation for multiple runs compared to standard versions. Modified versions of the artificial bee colony optimisation algorithm, genetic algorithm, grey wolf optimisation algorithm, and particle swarm optimisation algorithm are tested and compared for the optimal sizing of two operational amplifier topologies. An extensive performance evaluation of all the modified algorithms showed that the modifications have resulted in consistent performance with improved convergence for all the algorithms. The implementation of parallel computation in the algorithms has reduced run time. Among the considered algorithms, the modified artificial bee colony optimisation algorithm gave the most optimal solution with consistent results across multiple runs.

Current Re-Use Architecture and Pre-Distortion Technique Employing Re-Configurable Low Noise Amplifier for the Design of Nano-Electronic Sensors

This study presents the design of reconfigurable CMOS Low Noise Amplifier (LNA) topologies to achieve acceptable linearity, gain, and low noise for Nano-sensor applications. The frequency bands at 2.4 GHz, 5 GHz and 28 GHz are taken into consideration for employing the Pre-distortion and current reuse technique. Millimeter Wave (MMW) frequency bands include excellent impedance matching, good isolation between the ports, To improve the futuristic applications of RADAR sensors, low noise figures and significant gain are preferred. The designed re-configurable structure achieved At 2.4 GHz, the gain is modest with a low NF of 2.6 dB, less than 2 dB at 5 GHz, and more than 10 dB at 28 GHz frequencies. The Stability of the amplifier greater than 1 dB, The arrangement of the layout with a chip measuring 0.5×0.2 mm2 and a moderate power increase make it appropriate for nanosensor creation.

A Power-Efficient Linearized Open-Loop OTA Utilizing Reconfigurable Tail-Resistor Pair

This brief presents a power-efficient open-loop operational transconductance amplifier (OTA) topology for sensing applications. Reconfigurable tail-resistor (RTR) technology is proposed to achieve exceptional odd-order harmonic distortion while maintaining excellent energy-efficiency to meet the different application needs of sensors. The key to achieving this performance is the reconfigurability of resistors based on switches and the degeneration of resistors for the exponentiation of transistors in sub-threshold region. Fabricated in a 180-nm CMOS technology, the prototype linearized OTA achieves -82-dB third harmonic suppression for an input signal of 100-mVin-diff employing the pseudo-differential degeneration configuration, and exhibits -77.6-dB linearity in the commonmode degeneration topology. And it only dissipates 3.6-lW from 1.35-V/1.8-V supply.

A 32-GHz Eight-Way Power Amplifier MMIC in 150 nm GaN HEMT Technology

This paper presents a 32 GHz high-power amplifier (HPA) with a design strategy to achieve high-power output with reliable operation for Ka-band deep space satellite communication in 150 nm GaN HEMT technology. The presented Ka-band HPA employs a cascaded two-stage common source amplifier topology, and the output stage comprises an eight-way power combining network in the current mode. The interstage matching network is designed with the bandpass configuration utilizing capacitors and transmission lines to provide better stability at the low-frequency regime. The implemented Ka-band HPA achieved a power gain of 7.3 dB at the input level with the maximum PAE at 32 GHz, and the 3 dB gain bandwidth was 3.5 GHz (31.3~34.8 GHz). The saturated output power at the peak power-added efficiency (PAE) of 19.3% was 38.2 dBm, and the output 1 dB gain compression point (OP1 dB) was 27.4 dBm in the measurement. The designed HPA consumes an area of 19.35 mm2 including RF pads and DC pads.

A genetic‐algorithm‐based synthesis of microwave integrated distributed amplifiers

AbstractThis article presents a genetic algorithm‐based technique for microwave integrated distributed amplifier synthesis. To speed‐up synthesis, only linear characteristics are used in the goal function. The technique uses MMIC foundry process design kit models providing manufacturing‐ready schematics to be found. The models from the process design kit are presented as S‐parameters again to enhance algorithm performance. The technique allows searching among most of the existing schematics of the microwave distributed amplifier but is not limited to typical topologies. The section number is theoretically unlimited and makes it possible to find principally new circuit topology. The synthesis shortens and simplifies the distributed amplifier design time. Experimental validation of the technique is carried out by synthesizing the broadband driver stage for the 20–30 GHz buffer amplifier. The technique produces several amplifier topologies meeting the requirements. The most appropriate circuit was manufactured using a commercial 0.25 μm GaAs pHEMT process. The manufactured buffer amplifier demonstrates a gain of 10 dB and 20 dBm output power at a 1 dB compression point.

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS.

This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.

Millimeter-Wave CMOS Low-Noise Amplifier With High Gain and Compact Footprint

For millimeter-Wave (mm-Wave) communications, this letter proposes a low-noise amplifier (LNA) topology by using gain-boosting and negative feedback techniques. In the proposed two-stage LNA, the first stage combines these two techniques to achieve a trade-off between gain and bandwidth. Following that, in the cascode structure, inductors are used to compensate for the parasitic capacitance of the transistors. To validate the proposed topology at a low cost, an mm-Wave LNA is designed and fabricated in a 180 nm CMOS process. Using two stages only, it achieves a maximum gain of 14.1 dB at 24.8 GHz, which is comparable to that of classical LNAs with three stages, and the chip footprint is reduced by 43%.

160 GHz D-Band Low-Noise Amplifier and Power Amplifier for Radar-Based Contactless Vital-Signs-Monitoring Systems.

This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157-166 GHz frequency band. The -3 dB gain bandwidth corresponded to 157-166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the -3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively.

Wireless Piezoelectric Motor Drive

Nanopositioners with embedded piezoelectric motors are used in a variety of industries, from microscopy to laser processing or measurement systems. A concrete example would be fine-tuning of multiple mirror or lens units in a system. After fine adjustment of a mirror or lens, its position is expected to be maintained when the system is not energized. Features such as small size, direct drive, and maintaining position with high rigidity at power off make inertia-type piezoelectric motors suitable for such “set and go”-type applications. However, wiring with dedicated control electronics for each positioner can increase system complexity. In this study, a wireless driving method for piezoelectric inertia-type motors is introduced for the first time, to the best of our knowledge. In our approach, sawtooth signals for driving a two-phase piezoelectric inertia motor are converted into two complementary pulse-width-modulated (PWM) signals at 1.0 MHz and amplified by class-D amplifier topology, in which GaN transistors are implemented. The amplified complementary PWM signals are applied to a transmitter coil. A receiver coil, which forms an LC network with the capacitances of the piezoelectric multilayer actuators, picks up the driving signals. The filtered voltage waveform by the receiver coil is converted into a modified sawtooth signal, which can operate the piezoelectric inertia-type motor wirelessly. Initial measurements revealed that even a single driving pulse can be transmitted to the receiver coil and precise movements of the slider can be obtained. Mean step sizes for single pulse drive are 140 nm in one direction and 125 nm in the reverse direction.