Amorphous Thin-film Transistors Research Articles

Performance Improvement of Amorphous Thin-Film Transistors With Solution-Processed InZnO/InMgZnO Bilayer Channels

We present a dual active layer structure composed of indium–zinc oxide (InZnO) and indium–magnesium–zinc oxide (InMgZnO), which is fabricated using a simple solution process. By utilizing a heterojunction structure, combined with the high mobility of the front channel (InZnO) and the low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\textsc{off}}$</tex-math> </inline-formula> -state current of the back channel (InMgZnO), we are able to achieve thin-film transistor (TFT) devices with enhanced performance and greater stability. Finally, we are able to optimize the device by optimizing the front channel thickness and treating the heterojunction interface with oxygen plasma, achieving a mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu_{\text{sat}}$</tex-math> </inline-formula> ) of 5.94 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\text{2}$</tex-math> </inline-formula> /( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$</tex-math> </inline-formula> ), a threshold voltage of 0.98 V, an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\biosub{on}}$</tex-math> </inline-formula> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\biosub{off}}$</tex-math> </inline-formula> ratio of 7.49 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\text{8}$</tex-math> </inline-formula> , and a subthreshold swing (SS) of 325 mV/decade. Furthermore, the device maintains almost unchanged hysteresis voltage and exhibits high bias stability, which is demonstrated by the minimal threshold voltage variation of only 0.27 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 0.21 V under positive gate bias (PBS) and negative gate bias (NBS) for 1 h, respectively. The high electrical performance and stability of heterojunction TFTs can be attributed to the reduced interfacial defect state achieved through oxygen plasma treatment, as well as the electron redistribution occurring at the heterojunction interface.

Characterization and modeling of threshold voltage for organic and amorphous thin-film transistors

This work portrays the study and analysis of several extraction techniques that are typically used to ascertain the threshold voltage of organic thin-film transistors (OTFTs) and oxide-based transistors. This study evaluates the effects of physical and electrical parameters such as channel length, doping concentration, temperature, and trap on the threshold voltage (VTH) of both p-type and n-type bottom gate top contact (BGTC) OTFTs using graphical method. The methods employed in the present work to extract the threshold voltage are determined in the linear region of operation and are derived from the drain current (IDS) and the gate-source voltage (VGS) transfer characteristics. To compare and analyze the threshold voltage, various techniques such as the linear extrapolation method (ELR), constant current method (CC), transconductance linear extrapolation method (GMLE), second derivative method (SD), ratio method (RM), Inverse Ratio method (VX), and transition method (TM) are employed in the present work. In addition to DC characterization, the capacitance-voltage (C-V) method was also used to extract and compare the threshold voltage using all the conventional techniques listed above. 2-D numerical simulations were performed to assess the validity and usefulness of the various methodologies used for the extraction of the threshold voltage.

A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.

An insight to mobility parameters for AOSTFTs, when the effect of both, localized and free carriers, must be considered to describe the device behavior

The relation between the empirical mobility model parameters used for amorphous thin film transistors and physical device parameters is analyzed, when both localized and free carriers have to be considered to represent the device behavior. A simple procedure is presented to obtain the characteristic temperature and trap concentration of the DOS at the conduction band, using only the linear transfer characteristic at room temperature. An empirical analytical expression that represents analytically the dependence of the surface potential on the gate voltage is presented and validated. Using this expression, the procedure described to calculate the above mentioned parameters is completely analytical. The procedure presented is applied to experimental data of a-IGZO TFTs fabricated with two different technological process.

TiOx-based thin-film transistors prepared by femtosecond laser pre-annealing

We report on thin-film transistors (TFTs) based on titanium oxide (TiOx) prepared using femtosecond laser pre-annealing for electrical application of n-type channel oxide transparent TFTs. Amorphous TFTs using TiOx semiconductors as an active layer have a low-temperature process and show remarkable electrical performance. And the femtosecond laser pre-annealing process has greater flexibility and development space for semiconductor production activity, with a fast preparation method. TFTs with a TiOx semiconductor pre-annealed via femtosecond laser at 3 W have a pinhole-free and smooth surface without crystal grains.

Bias-Dependent Effective Channel Length for Extraction of Subgap DOS by Capacitance–Voltage Characteristics in Amorphous Semiconductor TFTs

Bias-dependent effective channel length [ $L_{\mathrm {eff}}(V_{G})]$ is empirically modeled with a channel conduction factor [ $\alpha (V_{G})]$ for a consistent capacitance–voltage ( $C$ – $V$ ) characterization of the intrinsic subgap density of states (DOS) over the bandgap with the sub-bandgap photoresponsive $C$ – $V$ technique in amorphous thin-film transistors. We define the effective channel length $L_{\mathrm {eff}}(V_{G})$ through the product of the empirical channel conduction factor [ $\alpha (V_{G})]$ and the metallurgical channel length ( $L_{m})$ . We confirm that the gate bias-dependent channel conduction effect is significant in the subgap DOS far from the conduction band edge ( $E_{C})$ due to the low conductivity of the channel under subthreshold bias.

Dual-Sweep Combinational Transconductance Technique for Separate Extraction of Parasitic Resistances in Amorphous Thin-Film Transistors

We report a dual-sweep combinational transconductance technique for separate extraction of parasitic source (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) and drain (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) resistances in thin-film transistors (TFTs) by combining forward and reverse transfer characteristics. In the proposed technique, gate bias-dependent total resistance [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TOT</sub> (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> )] and degradation of the transconductance due to the parasitic resistance at the source terminal during the dual-sweep characterization are employed. Applying the proposed technique to amorphous oxide semiconductor TFTs with various combinations of channel length (L) and width (W), we successfully separated R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> . A model for the W- and L-dependences of the extracted parasitic resistances is also provided.

Effect of double-layered Al2O3/SiO2 dielectric materials on In–Ga–Zn–O(IGZO)-based amorphous transparent thin film transistors

A double-layered Al2O3/SiO2 dielectric structure was applied to In–Ga–Zn–O-based amorphous thin film transistors through the atomic layer deposition (ALD) of aluminum oxide combined with thermally grown SiO2 dielectrics. The presence of ALD-based Al2O3 increased the on/off current ratio, decreased the sub-threshold slope, and decreased the threshold voltage. However, the addition of Al2O3 increased the turn-on voltage and slightly and adversely decreased the mobility. The device features appear to be associated with the presence of high-k Al2O3, which results in newly formed interfaces, oxide integrity, and high charge storage capabilities. The performance of the optimized thin film transistor is shown with the 50nm Al2O3/50nm SiO2 dielectric structure, which has a threshold voltage of 8.67V, a turn-on voltage of 5.09V, an on/off current ratio of 5.12×109 and a sub-threshold slope of 0.23V/decade.

High Performance of Y-doped Sn-Zn-O Films Fabricated by Solution-process for Amorphous Thin Film Transistors

ABSTRACTThe effect of Y dopant incorporated into ZTO with different Y ratios in Y-ZTO system on the performances of ZTO-based TFTs is investigated by using sol-gel process. The proper Y doped ZTO present both high film crystallization temperature and superior electrical properties as an active channel layer of TFTs. The fabricated YZTO-based TFTs with 11% Y show the excellent devices performance such as the channel field effect mobility of 1.756 cm2/Vs, SS of 2.13 V/dec, threshold voltage of 0.8V and on/off ratio of 3.12×106.

Unified Subthreshold Coupling Factor Technique for Surface Potential and Subgap Density-of-States in Amorphous Thin Film Transistors

We report a unified subthreshold coupling factor technique for a simultaneous extraction of the surface potential $(\psi_{\rm S})$ and the subgap density-of-states [DOS: $g(E)$ ] over the bandgap in amorphous semiconductor thin film transistors (TFTs). It is fully based on the experimental gate bias-dependent coupling factor $[m(V_{\rm GS})]$ under subthreshold bias. Through the proposed technique only with current-voltage data under subthreshold operation, a unified extraction of the DOS with a consistent mapping of the gate bias $(V_{\rm GS})$ to the subgap energy is obtained. Applying to amorphous InGaZnO TFTs, $g(E)$ is obtained to be a superposition of two exponential functions with $N_{\rm TA}=1.62\times 10^{17}~{\rm eV}^{-1}~{\rm cm}^{-3}$ and $kT_{\rm TA}=0.026~{\rm eV}$ for the tail states while $N_{\rm DA}=6.5\times 10^{16}~{\rm eV}^{-1}~{\rm cm}^{-3}$ and $kT_{\rm DA}=0.22~{\rm eV}$ for the deep states.

Capacitance–Voltage Measurement With Photon Probe to Quantify the Trap Density of States in Amorphous Thin-Film Transistors

We report on a characterization method to quantitatively estimate the interfacial trap density of states (DOS) in thin-film transistors (TFTs): photon-probe capacitance-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> ) measurement. The photo- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> method was compared to photoexcited charge-collection spectroscopy, which is another photon-probe method using current-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) measurement to meet the same purpose. Here, we directly characterized the DOS of amorphous-Si- and amorphous-InGaZnO-based TFTs using the photon-probe <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> measurement, and the results turned out to mainly focus the trap DOS at channel/dielectric interface. On the one hand, the DOS profile by photon-probe <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> method appeared to give additional trap information from the transistor back channel.

Using Fluorine-Ion Implanted a-Si Layer to Reduce Ni Contamination and Passivate the Defects in NILC Poly-Si

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in active matrix organic liquid crystal displays (AMOLCDs) because their higher carrier mobility and lower threshold voltage than conventional amorphous thin-film transistors (a-Si TFTs). Ni-metal-induced lateral crystallization (NILC) is one of these effective methods that can reduce the crystallization temperature to fabricate poly-Si TFTs on inexpensive glass substrates. However, the poly-Si grain boundaries which included dangling bonds would trap Ni and NiSi2 precipitates. This phenomenon resulted in threshold voltage shifting and lower field-effect mobility. In order to reduce the Ni contamination and passivate the dangling bonds in the active layer, the a-Si layer with fluorine-ion implanted was used as gettering layer (F-G layer) to resolve the issue. In the gettering process, Ni precipitates would diffuse to the fluorine-ion implanted a-Si layer because of the concentration gradation difference. Concurrently, fluorine-ion also diffused into the active layer and passivated the dangling bonds which associated with trap states density.

Gate-bias stress in amorphous oxide semiconductors thin-film transistors

A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3×105 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites.

New procedure for the extraction of a-Si:H TFTs model parameters in the subthreshold region

In a previous paper we presented a new procedure to extract basic AIM-Spice model parameters of amorphous thin film transistor model in the above-threshold region, based on the integration of the experimental data current. In this paper we present a new procedure to determine subthreshold TFT parameters highly dependent on the fabrication technology as the density of deep states and characteristic temperature of deep states. These parameters are extracted in a simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model parameter. Other parameters required for device modeling in the subthreshold regime are also determined. The validity of the procedure is tested for a-Si:H TFTs with channel length down to 4 μm. We also show the good coincidence between calculated, using parameter values obtained with our new extraction procedure and experimental curves, in all working regions of the devices. Finally we discuss effects in the behavior of I DS vs. V DS curve related to the series resistance at the drain and source, which become evident during the device modeling.

New procedure for the extraction of basic a-Si:H TFT model parameters in the linear and saturation regions

A new procedure is proposed to extract basic parameters for the AIM-Spice amorphous thin film transistor model in the above-threshold region. Our method avoids non-linear optimization, which is mainly the method utilized up to now, when using a program extractor included in AIM-Spice. The present extraction procedure is based on the integration of the experimental data current. The integration method as in known is convenient to decrease the effects of experimental noise. The method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold parameters. The accuracy of the simulated curves using the parameters extracted with the new procedure is verified with measured and calculated data using the expressions contained in the model.

The effect of back channel hydrogen plasma treatment on the electrical characteristics of amorphous thin film transistors

This letter reports that hydrogen plasma treatments on the back channel of thin film transistors are an effective way to improve the off-current characteristics. The effects of the hydrogen plasma treatments on the amorphous Si were checked using current–voltage plotter, atomic force microscopy, and secondary ion mass spectrometry. The surface of the amorphous Si was etched and passivated by the hydrogen radicals at various radio-frequency (rf) powers. The resistance of the modulated back channel increased and the off-current characteristic was improved from 530 to 1.68 pA, which was caused by the increase of roughness and hydrogen contents at back channel as a function of rf power.

1/f noise investigations in small channel length amorphous silicon thin film transistors

Conduction and low-frequency noise are analyzed in hydrogenated amorphous thin film transistors with small channel length. From current–voltage characteristics a set of conduction parameters is extracted pointing out parasitic resistances in series with the active channel. The low-frequency noise behavior is studied by means of the small equivalent circuit of the device. Intrinsic channel noise is separated from access resistance noise. Channel noise variations versus device biases agree with Hooge’s theory (carrier mobility fluctuations) but the noise levels are greater than in crystalline metal-oxide-semiconductor transistors. For high drain current 1/f noise in access series resistances prevails and becomes the main noise source. So, the results show the important part taken by these resistances in conduction and noise. Some comments for the design of thin film transistors are given.

Liquid‐crystal display cell model using piecewise approximations

AbstractThe dynamic characteristics of the capacitance of liquid‐crystal display (LCD) pixel constituting the active matrix LCD device using amorphous thin film transistors (TFTs) have been analyzed; an electrically equivalent circuit model is proposed based on the obtained results. The model consists of nonlinear resistors and dynamic elements such as capacitors or inductors and can represent the voltage and time dependence of the capacitance value in the LCD pixel. The proposed model is incorporated into the circuit simulator SPICE as a built‐in model.

Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors

The threshold voltage instabilities in nitride/oxide dual gate dielectric hydrogenated amorphous silicon (a-Si:H) thin-film transistors are investigated as a function of stress time, stress temperature, and stress bias. The obtained results are explained with a multiple trapping model rather than weak bond breaking model. In our model, the injected carriers from the a-Si:H channel first thermalize in a broad distribution of localized band-tail states located at the a-Si:H/aSiNx:H interface and in the a-SiNx:H transitional layer close to the interface, then move to deeper energies in amorphous silicon nitride at longer stress times, larger stress electric fields, or higher stress temperatures. The obtained bias-stress-temperature induced threshold voltage shifts are accurately modeled with a stretched-exponential stress time dependence where the stretched-exponent β cannot be related to the β=TST/T0 but rather to β≂TST/T0*−β0 for TST≤80 °C; for TST≥80 °C, the β is stress temperature independent. We have also found that β is stress gate bias independent.

Effect of SiOxNy gage insulator on amorphous silicon thin-film transistors

The effect of the plasma chemical vapor deposition SiOxNy gate insulator on the threshold voltage for amorphous thin-film transistors was investigated, using different compositions of SiOxNy. The density of trapped charges responsible for the threshold voltage shift was found to be minimum at x/y=0.58. Photoluminescence measurements reveal that the peak energy in the photoluminescence in SiOxNy layers has a maximum value at x/y=0.58. The threshold voltage (Vth) was also found to increase with further increase of x/y. The observed threshold voltage shift is qualitatively interpreted in terms of energy band at the insulator-silicon interface.