Amorphous Silicon Gate Driver Circuit Research Articles

A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry

In this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.

Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

ABSTRACTA short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuit-simulation-based multi-objective evolutionary algorithm on the unified optimization framework . The ASG circuit was optimized for the following given specifications: rise time <0.7 µs; fall time <0.6 µs; ripple peak <6.5 V; clock Ctotal <40 pf; and total TFT widths <6000 µm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively.

Low Power and High Driving Capability of Amorphous Silicon Gate Driver Circuit

In this paper, we propose a novel amorphous silicon gate driver (ASG) circuit with useful driving methods in saving power consumption and improving driving capability as well. Unlike other driving methods that are used to improve the driving capability also increases the power consumption strikingly. In this paper, an ASG circuit with novel driving method is proposed and realized in standard 5-mask hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) process. The circuit consisting of 13 a-Si:H TFTs is used in portable flat-panel displays (FPDs) for the high driving capability and low power characteristic. By comparing other driving methods, the results of the definitive measurement show that the minimum driving high voltage is improved with 2 volts increment and the power consumption increases 9.7% slightly. Moreover, the other dynamic characteristics of the ASG, such as the rise time and fall time of the outputs, can be improved at the same time. To validate the results, the designate circuit is fabricated with 5- $\mu$ m a-Si:H TFT process and the experimental results confirm the practicability of achieved design. Three different driving methods are adopted in the same ASG circuit to respond three individual output characteristics.

Circuit-Simulation-Based Multi-Objective Evolutionary Algorithm for Design Optimization of a-Si:H TFTs Gate Driver Circuits Under Multilevel Clock Driving

This work optimizes dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator running on the platform of unified optimization framework (UOF). The ASG driver circuit consisting of 17 a-Si:H TFTs is optimized for the given specifications of the fall time ${ $\mu$ s and the ripple voltage ${ 9 V while simultaneously minimizing the total layout area. More than 50% reductions on the fall time of the ASG driver circuit have been achieved by using the optimization methodology together with a novel three-level clock driving technique. The measured results of the fabricated sample using the optimized parameters confirm the practicability of reported MOEA methodology.

Design, Fabrication and Characterization of Low-Noise and High-Reliability Amorphous Silicon Gate Driver Circuit for Advanced FPD Applications

We report a novel design of amorphous silicon gate (ASG) driver circuit with not only low output noises but also improved reliability. The ASG circuits are made of thin-film transistors (TFTs) and integrated in the substrate glass. Unlike the most traditional ASG circuits, the proposed pull-down signals are complementary with lower frequency to discharge the critical nodes in the proposed circuit. The new pull-down signals are created to discharge each two adjacent stage circuits. By inputting two controlled pulse signals, the prospective pull-down signals can be created eventually in the circuit. To simulate the real driving conditions, a string of a resistance (1.24 ${\hbox{k}}\Omega$ ) and a capacitance (85.5 pF) are connected to each output as loading. By probing the output pads of the real circuit sample, the output characteristics can practicably be measured. In particular, the output ripples can be suppressed to 0.28 V. Moreover, the measured threshold voltage $({\rm V}_{\rm th})$ shift with two stressing signals at different frequencies reveals the significant difference. The measured ${\rm V}_{\rm th}$ shift after 12 h of the clock stressing with lower frequency (167 Hz) is about 12% slower speed than that of the stressing clock with higher frequency (16.7 kHz) under the high temperature (60 $^{\circ}\hbox{C}$ ).

High-reliability and low-noise amorphous-silicon gate with a novel clock-driving methodology

In this paper, for the first time, a novel amorphous-silicon thin-film transistor gate drive circuit and its successfully improved dynamic characteristics are presented. Not only was the output ripple suppressed; the rate of threshold voltage shift was also reduced by up to 20%. About 50% power-saving was also estimated. The amorphous-silicon gate driver circuit was further fabricated, and the measured results show the high practicability of the achieved design.

6.3: Distinguished Paper: A 9‐inch Flexible Color Electrophoretic Display with Projected Capacitive Touch Panel and Integrated Amorphous‐Silicon Gate Driver Circuits

AbstractIn order to bring Ebook reader to the next stage, we have developed a prototype and concept design that combine flexible color electrophoretic display (EPD), flexible projected capacitive touch panel (TP) and amorphous‐silicon gate driver circuit on array (GOA) technologies. This prototype has been fabricated successfully with the white reflectivity of 23.5%, contrast ratio of 16:1 and 16 gray‐level color images. In terms of the flexible TP, it is capable of detecting multi‐touch events and transmittance is more than 73.2%. GOA circuit operation is also verified with a 9‐inch flexible color EPD.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

P‐204L: Late‐News Poster: A Stable Amorphous Silicon Gate Driver Circuit with Continual Pulse Triggering Method

AbstractInstability of amorphous silicon TFT has been a major challenge in designing a shift register of gate driver. We proposed in this paper a novel amorphous silicon gate driver (ASG). A 2.8 inch QVGA TFT‐LCD prototype driven by proposed ASG has been successfully fabricated. Stable operation within 240 hours at 70 °C temperature has been demonstrated without noticeable failure or artifacts.

16.1: Distinguished Paper: Rollable Electrophoretic Display with Amorphous‐Silicon Gate Driver Circuit Integrated

AbstractHighly flexible electrophoretic display with gate driver circuits integrated was demonstrated. Beginning from the essential components such as TFTs, resistors and capacitors, the authors finally design a GOA‐embedded display which can withstand 10,000 rolling cycles of 20 mm radius without any line defect and optic performance degradation.