Amorphous Si Thin Film Transistors Research Articles

Dangling-bond defect state creation in microcrystalline silicon thin-film transistors

We analyze the threshold voltage shift in microcrystalline Si thin-film transistors (TFTs), in terms of a recently developed thermalization energy concept for dangling-bond defect state creation in amorphous Si TFTs. The rate of the threshold voltage shift in microcrystalline Si TFTs is much lower than in amorphous Si TFTs, but the characteristic energy for the process, which we identify as the mean energy to break a Si–Si bond, is virtually the same. This suggests that the same basic Si–Si bond breaking process is responsible for the threshold voltage shift in both cases. The lower magnitude in microcrystalline Si TFTs is due to a much lower attempt frequency for the process. We interpret the attempt frequency in amorphous and microcrystalline silicon in terms of the localization length of the electron wave function and the effect of stabilizing H atoms being located only at grain boundaries.

The impact of self-aligned amorphous Si thin film transistors on imager array applications

Laser processing allows the fabrication of self-aligned amorphous Si thin film transistors (a-Si:H TFTs). These devices have much smaller parasitic capacitance between gates and source/drain contacts and can have much shorter channel lengths compared to the conventional a-Si:H TFTs. We have fabricated matrix-addressed, optical imager arrays using these new a-Si:H TFTs as pixel switches. We also have demonstrated that four-phase dynamic shift registers using short channel a-Si:H TFTs can be operated at a clock speed of 400 kHz (less than 0.625 μs for each clock phase), indicating the possibility of integrating some of the peripheral circuits based on a-Si:H TFT technology. The advantages of using self-aligned a-Si TFTs as pixel switches in large-area, flat-panel imagers are discussed. Improved noise performance is expected for large area imager arrays.

Electrical Instabilities and 1/f Noise in Organic Pentacene Thin Film Transistors

ABSTRACTWe report on the influence of Bias-Temperature Stress (BTS) on the pentacene Thin Film Transistors (TFTs) electrical characteristics and on their 1/f noise level. The gate BTS primarily affects the TFT threshold voltage, leaving both mobility and sub-threshold slope values almost unchanged. The degree of the threshold voltage shift induced by the positive or negative BTS depends on the TFT design and the BTS parameters. The current-voltage characteristics time dependence of the organic TFTs, subjected to the BTS, resembles that for amorphous-Si TFTs. The results of the 1/f noise measurements in the organic TFTs allowed us to conclude that the gate BTS primarily affects the TFT contact regions, resulting in the increase of both the contact noise and the contact resistance.

1/f Noise Behavior in Pentacene Organic Thin Film Transistors

ABSTRACTWe studied the low frequency noise in top-contact pentacene Thin Film Transistors (TFTs). The relative spectral noise density of the drain current fluctuations SI/I2 had a form of 1/f noise in the measured frequency range 1Hz - 3.5kHz.Our studies of the noise dependencies on the gate-source VGS and drain-source VDS voltages showed that the dependencies differed from those observed for conducting polymers and resembled those reported for crystalline Si n-MOSFETs.To compare the device noise level with those of other devices and materials, we extracted the Hooge parameter α. In order to calculate the total number of carriers we used a model simulating the device DC characteristics, similar to that for amorphous Si TFTs. The extracted Hooge parameter was 0.04. For an organic material this is an extremely small value, which is three orders of magnitude smaller that the Hooge parameter values reported for conducting polymers and only several times higher than the values for amorphous Si TFTs.

Application of Self-Aligned Amorphous SI Thin-Film Transistors

AbstractWe have successfully used self-aligned Amorphous Si Thin-Film Transistors, fabricated by a laser doping/annealing process, to construct dynamic shift register circuits, which can be used as gate-line drivers or in other peripheral circuits for flat-panel displays and imagers. Taking advantage of easily scaling down the TFT channel length in a self-aligned process, much higher circuit speeds can be achieved compared to that of circuits using conventional TFTs. We have successfully demonstrated a four-phase dynamic shift register, operating at a clock speed higher that 250 kHz (1 μs for each clock phase) built on 3 μm channel length TFTs. This new technology opens up possibilities for integrating peripheral circuits in flat-panel displays and imagers based on a-Si TFTs.

Integration of organic LEDs and amorphous Si TFTs onto flexible and lightweight metal foil substrates

We report the integration of organic light emitting devices (OLEDs) and amorphous Si (a-Si) thin-film transistors (TFTs) on both glass, and unbreakable and lightweight thin stainless steel foil substrates. The doped-polymer OLEDs were built following fabrication of driver TFTs in a stacked structure. Due to the opacity of the steel substrate, top-emitting OLED structures were developed. It is shown that the a-Si TFTs provide adequate current levels to drive the OLEDs at video brightness (/spl sim/100 cd/m/sup 2/). This work demonstrates that lightweight and rugged TFT backplanes with integrated OLEDs are essential elements for robust and highly portable active-matrix emissive flat-panel displays.

History and Trend of Giant Microelectronics

AbstractGiant microelectronics is defined as technology which forms electronic devices with fine structures on a large‐area substrate such as a glass. They are applied to image input/output (I/O) devices of active‐matrix liquid‐crystal displays, printer heads, and image sensors. The thin‐film transistor (TFT) is the typical device formed on such a large‐area substrate. It has been developed since the 1960s, realized for practical applications in the 1980s, and will be used widely in the 1990s.For active‐matrix liquid‐crystal displays, amorphous Si TFTs which are formed at low temperature by plasma CVD have been used. Recently, these displays have begun to be used for personal computers. However, the cost reduction of these displays must be achieved by increasing the size of the substrate and throughput of the products. At the same time, the integration of the driver circuits using the low‐temperature polycrystalline Si TFT must be carried out.Japan is a leader in the production of giant electronics devices. However, to establish this technology, international cooperation will be important.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

A low-temperature poly-Si thin-film transistor (TFT), having inverted-staggered structure, has been developed successfully using excimer laser annealing and ion doping. This TFT is suitable for pixel transistors of large-area and high-resolution LCDs. The maximum process temperature of the TFT fabrication steps is less than 450°C, so the same glass substrate on which amorphous Si TFT arrays are formed can be used in this poly-Si TFT process. Furthermore, most of the procedures, equipment and thin-film materials used to fabricate amorphous Si TFTs are compatible with fabrication of the poly-Si TFTs. On the other hand, some investigation of the CMOS driver circuit has been done, and it has been found that the threshold voltage of these poly-Si TFTs can be controlled easily by lightly doping of B ion into the channel region using the ion doping system.

Process compatibility in integrated processing of semiconductor devices in multichamber systems

This paper reviews recent results with respect to formation of heterostructure devices in multichamber processing environments with in vacuo surface analysis diagnostics and in situ process monitoring. The emphasis is on the formation of two types of thin film device structures (i) gate stacks for metal–oxide–semiconductor (MOS) devices, including field effect transistors (FETs) and (ii) semiconductor thin film devices including amorphous Si thin film transistors (TFTs) and p-i-n diodes. Thin films of the dielectric and semiconductor materials for these structures have been deposited by low-temperature, remote plasma-enhanced chemical vapor deposition (PECVD). A key step in the processing of these devices is the formation of electronically active interfaces between the various constituent layers. For the MOS structures this generally requires preparation of the semiconductor substrate prior to the deposition of the dielectric film. Our studies indicate that this final substrate processing step is crucial to electrical quality the semiconductor/dielectric interface, and should generally be performed in the same chamber as the dielectric deposition. This observation has prompted us to re-evaluate design criteria for the individual processing chambers in multichamber systems in the context of requiring that chambers dedicated to film deposition should also provide the internal fixtures, gas flow and pressure control that are necessary for substrate processing as well as film deposition.

The effect of lead impurity on amorphous Si thin film transistors

The effect of lead impurity on amorphous Si thin film transistors

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.