Amorphous Oxide Semiconductor Thin-film Transistors Research Articles

The Electronic Impact of X-Ray on Atomically-Thin Oxide Semiconductor Devices

In the past few years, there has been a significant emphasis on atomically-thin metal oxide semiconductors (OS), driven by their adjustable electrical properties that open up a range of electronic applications [1.2]. However, the mechanisms of transport and electronic tunability in OS remain unclear [3]. X-ray characterization techniques, i.e. X-ray photoelectron spectroscopy (XPS) and X-ray diffractometer (XRD), are considered as non-destructive and are widely used to quantify the chemical and electronic state of OS. In this work, we discovered that X-ray has significant impact on the electronic properties of OS. We observed that low energy X-ray (<2 keV) induces a negative V T offset in OS devices [4]. The variation in V T primarily originates from the chemical interaction of oxygen molecules on the channel surface. OS devices absorb the low-energy X-ray, generating the holes, and they subsequently react with O2 - on the channel surface, resulting in the production of oxygen and its removal from the channel surface, as shown in Fig 1a. The V T shift caused by low energy X-ray will recover in air over time, as illustrated in Fig 1b. We incorporated the post low-energy X-ray devices into a vacuum environment with a pressure of 10-6 torr, and the V T of the device exhibited no recovery over time, providing additional support for oxygen absorption mechanism. Time-resolved electrical measurements conducted in different atmospheric conditions reveal that the variations in V T arise from the oxygen absorption mechanism. The research highlights the effect of X-ray on OS and analyzes the mechanism behind the increase in OS carrier concentration induced by the X-ray exposure.[1] Si, M. et al. Scaled indium oxide transistors fabricated using atomic layer deposition. Nat. Electron. 5, 164–170 (2022).[2] Charnas, Adam, et al. Extremely Thin Amorphous Indium Oxide Transistors. Adv. Mater. 2304044 (2023).[3] Conley, J. F. Instabilities in amorphous oxide semiconductor thin-film transistors. IEEE Trans. Device Mater. Rel. 10, 460–475 (2010).[4] Tseng, R., Wang, ST., Ahmed, T. et al. Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors. Nat. Commun. 14, 5243 (2023). Figure 1

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors.

Recently, the growing demand for amorphous oxide semiconductor thin-film transistors (AOS TFTs) with high mobility and good stability to implement ultrahigh-resolution displays has made tracking the role of hydrogen in oxide semiconductor films increasingly important. Hydrogen is an essential element that contributes significantly to the field effect mobility and bias stability characteristics of AOS TFTs. However, because hydrogen is the lightest atom and has high reactivity to metal and oxide materials, elucidating its impact on AOS thin films has been challenging. Therefore, in this study, we propose controlling the hydrogen quantities in amorphous InSnZnO (a-ITZO) thin films through thermal dehydrogenation to precisely reveal the hydrogen influences on the electrical characteristics of a-ITZO TFTs. The as-deposited device containing 15.69 × 1015 atoms/cm2 of hydrogen exhibited a relatively low saturation mobility of 18.1 cm2/V·s and poor positive bias stress stability. However, depending on the extent of thermal dehydrogenation, not only did the hydrogen quantity and interface defect density (DIT) decrease but also the conductivity and surface energy increased due to the rise in oxygen vacancies and hydroxyl groups in a-ITZO thin films. As a result, the a-ITZO TFT with a hydrogen amount of 4.828 × 1015 atoms/cm2 showed that the saturation mobility improved up to 36.8 cm2/V·s, and positive bias stress stability was remarkably enhanced. Hence, we report the ability to manage the hydrogen quantity with thermal dehydrogenation and demonstrate that high-performance a-ITZO TFTs can be realized when an appropriate hydrogen concentration is achieved.

Reliability issues of amorphous oxide semiconductor-based thin film transistors

This review summarizes and discusses existing literature on reliability issues of amorphous oxide semiconductor thin-film transistors. The investigation focuses on bias stress, electro-static discharge, bending, and radiation reliability.

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Low-Voltage Operated High DC Gain Amplification Stage Based on Large-Area Manufacturable Amorphous Oxide Semiconductor Thin-Film Transistor

The industry-standard amorphous metal–oxide–semiconductor (AOS) thin-film transistor (TFT) technology is demonstrated for making low-voltage high intrinsic gain devices. It is revealed by the technology computer-aided design (TCAD) simulation that, without need of making Schottky barrier contacts, large output resistance and high intrinsic gain can be achieved in a subthreshold regime for AOS TFTs. It is further proved by the measurement results with the fabricated AOS TFT from a Gen-4.5 manufacturing line. A simple single-stage zero- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{GS}}$</tex-math> </inline-formula> load amplifier is implemented as a proof of concept, achieving a voltage gain larger than 50 for weak signal detection at a supply voltage of 5 V.

Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

This study presents a technique for simultaneous and consistent extraction of the mobility enhancement factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) and the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> ) with parasitic source and drain resistances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> ) in amorphous oxide semiconductor (AOS) thin film transistors (TFTs). This technique allows for the extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> as well as the accurate extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $</tex-math> </inline-formula> with only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> characteristics of the saturation operation in a single AOS TFT. The proposed technique was applied to amorphous indium–gallium–zinc-oxide (a-IGZO) TFTs with various structures. For intentional asymmetry, we confirmed the consistency with an external resistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}} = \text{10}$</tex-math> </inline-formula> , 20, 30 k <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega$</tex-math> </inline-formula> ). Extracted parameters ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) by the proposed method were compared with parameters extracted by other methods for verification. Furthermore, the drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{D}}$</tex-math> </inline-formula> ) was well reproduced using the extracted parameters regardless of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}}$</tex-math> </inline-formula> .

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors

In recent years, high-k gate dielectrics have attracted increasing attention in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), due to the urge for stronger gate controllability in advanced applications of high integration density. In this work, the ultra-thin top-gate insulator of atomic-layer-deposited (ALD) HfOx was developed for the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs. Despite the good electrical characteristics of the 4-nm HfOx-gated a-IGZO transistor, its reliability is considerably poor and ascribed to the abundant interface defects, for example, oxygen vacancies. The interface reaction between HfOx and a-IGZO during the ALD process is clarified to be responsible for such defect generation. To prevent the oxygen-related reaction, the a-IGZO channel is pre-treated using the strong oxidizing plasma, contributing to significantly enhanced electrical stabilities. However, the further thinner HfOx would readily increase the gate leakage current, since the electron can easily tunnel through the ultra-thin HfOx due to the low conduction band offset between HfOx and AOS. The 4-nm ALD HfOx together with the pre-oxidization contributes to the optimal performance and stability of top-gate a-IGZO TFT.

Addressing the Conflict between Mobility and Stability in Oxide Thin‐film Transistors

Amorphous oxide semiconductor thin-film transistors (AOS TFTs) are ever-increasingly utilized in displays. However, to bring high mobility and excellent stability together is a daunting challenge. Here, the carrier transport/relaxation bilayer stacked AOS TFTs are investigated to solve the mobility-stability conflict. The charge transport layer (CTL) is made of amorphous In-rich InSnZnO, which favors big average effective coordination number for all cations and more edge-shared structures for better charge transport. Praseodymium-doped InSnZnO is used as the charge relaxation layer (CRL), which substantially shortens the photoelectron lifetime as revealed by femtosecond transient absorption spectroscopy. The CTL and CRL with the thickness suitable for industrial production respectively afford minute potential barrier fluctuation for charge transport and fast relaxation for photo-generated carriers, resulting in transistors with an ultrahigh mobility (75.5 cm2 V-1 s-1 ) and small negative-bias-illumination-stress/positive-bias-temperature-stress voltage shifts (-1.64/0.76V). The design concept provides a promising route to address the mobility-stability conflict for high-end displays.

Impact of the Source/Drain Electrode Process on the Mobility-Threshold Trade-Off for InSnZnO Thin-Film Transistors

In this work, the source/drain (S/D) electrode process is considered to have a great impact on the mobility (μFE)–threshold (Vth) trade-off for high-mobility amorphous oxide semiconductor (AOS) thin-film transistors. High-mobility AOS materials have worse oxygen-fixation ability compared to InGaZnO. In this work, we show that this is the case for the Mo S/D electrode process on InSnZnO channels and has a great impact on the mobility-threshold trade-off. Oxygen vacancy gradients are observed in the depth profile X-ray photoelectron spectroscopy analysis on InSnZnO after Mo S/D deposition and show a bigger change in oxygen vacancies (VO) between the surface and inner layers and thicker compared to InGaZnO. This leads to an obvious negative shift in Vth or even no switching characteristic. Postprocessing such as oxygen-plasma treatment can make Vth positive but degrade the μFE. In situ replenishing oxygen via adopting ITO S/D electrodes deposited in an oxygen-containing atmosphere facilitates the achievement of excellent overall electrical characteristics, with μFE up to 87.1 cm2/Vs, Vth ∼ −0.64 V, and Ion/Ioff ∼ 2.3 × 108.

High-performance a-ITZO TFTs with high bias stability enabled by self-aligned passivation using a-GaOx

Maintaining gate bias stability under negative bias stress (NBS) and positive bias stress (PBS) is a long-standing issue in amorphous oxide semiconductor thin-film transistors (TFTs). The passivation of the channel layer is crucial for improving device stability. We show that amorphous gallium oxide, which possesses appropriate energy levels (lower electron affinity and higher ionization potential) for indium–tin–zinc oxide (ITZO) TFTs, can be etched selectively by tetramethyl ammonium hydroxide-containing developers that enable self-alignment passivation, such as easy contact hole formation during the drain and source lithography processes. The self-aligned passivation process led to a-ITZO TFTs with high mobility (&amp;gt;50 cm2 V−1 s−1) and low subthreshold swing (&amp;lt;90 mV/dec). The threshold voltage shifts under NBS and PBS using a bias gate voltage of ±20 V for 1 h were −0.09 and 0.15 V, respectively. This passivation can obviate the need for the conventional CVD-derived passivation process by utilizing the DC sputtering of gallium oxide, which may reduce hydrogen issues.

An Analytical Drain Current Model of ZnO-Based Amorphous Oxide Semiconductor Thin-Film Transistors

An analytical one-piece drain current model of ZnO-based amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) is presented in this article. This model is able to solve the main obstacle in a lack of analytical and physics-based nonregional device modeling for AOSTFTs and is suitable to be implemented into circuit simulators. Based on the effective-charge-density approach, free carrier density and localized carrier density, including tail and deep states, are unified into total carrier density. Then, one-piece surface potential is derived analytically from equivalent 1-D Poisson’s equation described in an effective-charge-density approach. It is also possible that channel carrier mobility is calculated from the ratio between free carrier and effective total carrier densities. Furthermore, drain current expression is derived analytically and validated by experimental data. Good agreements of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics prove that the proposed model could serve as a useful simulation tool implemented into circuit simulators.

(Invited) Thin-Film Transistor Accumulation-Mode Modeling

Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.

Performance Enhancement of Solution-Processed SixSnyO TFTs using Solution Combustion Synthesis

Amorphous oxide semiconductors thin-film transistors (AOs TFTs) have gained interest over the years because of their advantages over a-Si and poly-Si transistors.In particular, tin oxide is used as a semiconductor material because of its abundance, low toxicity, and high intrinsic mobility. Performance-wise, tin oxide TFTs need improvement because the reported average mobility remains < 10 cm2/Vs.1 Previous research used silicon doping to reduce tin oxide’s oxygen vacancies and improve its performance as a semiconductor channel.Currently, SixSnyO TFTs are fabricated using vacuum process, but solution processing is important to realize large-scale and high-throughput electronics. Sol-gel method is one of the conventional routes to produce solution-processed metal oxides. However, it requires high temperature (≤500°C) to facilitate film densification which is not compatible with flexible substrates having low degradation temperatures. Among the approaches for low-temperature TFT fabrication, solution combustion synthesis (SCS) has garnered significant attention because of its simplicity and versatility.2 SCS uses the energy released by combustion to help the formation of more M-O-M networks in the film. Thus, there is no need to use high temperature to condense and densify the film. This study attempts to produce SixSnyO TFTs through solution processing for the first time. We investigated the effect of solution combustion synthesis to the quality of SixSnyO films. Next, we optimized the aging time and oxidizer to fuel ratio (ammonium nitrate to urea) to determine the films with better quality. For aging time optimization, SixSnyO precursors were stirred at RT for 24-h, 48-h, and 72-h. Lastly, we compared the TFT performance in terms transfer characteristics of SixSnyO TFTs fabricated by sol-gel and SCS annealed at the same temperature. Secondary ion mass spectrometry (SIMS) analysis was used to compare the carbon impurities present in both SixSnyO films. The sol-gel film contained higher amounts of carbon impurities, about an order of magnitude higher as shown in Figure 1. This proves that SCS provides extra energy to help degrade the carbon-containing compounds in the film. Carbon atoms are considered impurities that can introduce defects in the SixSnyO film. These defects are detrimental to the performance characteristics of the fabricated TFT device. In addition, the thickness of the films was determined using X-ray reflectivity. The SCS film is 15.70 nm-thick while the sol-gel film is 18.88-nm thick. Furthermore, optimization of the SixSnyO films via SCS revealed that oxidizer to fuel ratio affects the roughness and amount of M-O bonds formed in the film. The 3:1 ratio failed to produce a film while other ratios were successful in producing films. Although the film with 1:1 ratio has root mean square roughness (Rq) value of 0.380 nm, it contains depressions and voids. On the other hand, the film using a 1:3 ratio showed a uniform and even surface with Rq value of 0.377 nm. In addition, characterization of the two films through X-ray photoelectron spectroscopy (XPS) showed higher percentage of M-O bonds in the O1s spectrum (530.5 eV) for the film with 1:3 ratio. The values are 45.9% and 59.3% for 1:1 and 1:3 ratios, respectively. The amount of oxygen vacancy and H- containing compounds also decreased in the 1:3 film.SixSnyO TFTs were fabricated from both SCS and sol-gel methods. Both TFTs showed high off-current and highly negative Vth, as shown in Figure 1. Therefore, both TFTs still contain several defects which suggests that 3% Si doping may be insufficient and must be increased to produce a significant effect. The sol-gel fabricated TFT also showed lower drain current. Therefore, the low annealing temperature at 300 ˚C is insufficient to densify the film and reduce impurities. On the other hand, SCS-assisted fabrication showed higher mobility at 3.14 cm2/Vs – confirming that SCS provided additional energy to degrade impurities and improve the M-O network in the SixSnyO channel. In conclusion, we were able to produce SixSnyO TFTs with improved mobility using solution combustion synthesis. However, the high V th and high off-current issues need to be addressed by increasing silicon dopant addition and exploring other fuel options. But overall, we can confirm that SCS is beneficial in improving the quality of SixSnyO films annealed at 300 ˚C. In the future, this low temperature fabrication is important to realize flexible SixSnyO TFT devices.AcknowledgementsThis research was supported by NAIST foundation grant.References Chang, H., et al. ACS Applied Electronic Materials, 3(11), 4943–4949.Carlos, E., et al. Chemistry - A European Journal, 26(42), 9099–9125. Figure 1

A Threshold Voltage Model for AOS TFTs Considering a Wide Range of Tail-State Density and Degeneration

There have been significant differences in principle electrical parameters between amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and silicon-based devices for their distinct conduction mechanisms. Additionally, threshold voltage is one of the key parameters in device characterization and modeling. In this work, a threshold voltage model is developed for AOS TFTs considering the various density of exponential tail states below the conduction band, including degenerate conduction. The threshold condition is defined where the density ratio of free carriers to the trapped carriers reaches a critical value depending on the distribution parameters of tail states. The resulting threshold voltage expression is fully analytical and is of clear physical meaning, with simple parameter extraction methods. Numerical and experimental verifications show that this model provides appropriate values of threshold voltage for devices with different sub-gap tail states, which could be a useful method for identifying the threshold voltage of a large variety of AOS TFTs.

Thin-film transistor accumulation-mode modeling

Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.

Improved Performance and Bias Stability of Al2O3/IZO Thin-Film Transistors with Vertical Diffusion

Several studies on amorphous oxide semiconductor thin-film transistors (TFTs) applicable to next-generation display devices have been conducted. To improve the poor switching characteristics and gate bias stability of co-sputtered aluminum–indium–zinc oxide (AIZO) TFTs, we fabricate Al2O3/indium–zinc oxide (IZO) dual-active-layer TFTs. By varying the Al2O3 target power and oxygen partial pressure in the chamber during Al2O3 back-channel deposition, we optimize the electrical characteristics and gate bias stability of the Al2O3/IZO TFTs. The Al2O3/IZO TFTs, which are fabricated under 50 W Al2O3 target power and 13% oxygen partial pressure conditions, exhibit a high electron mobility of 23.34 cm2/V·s, a low threshold voltage of 0.96 V, an improved on–off current ratio of 6.8 × 107, and a subthreshold swing of 0.61 V/dec. Moreover, by increasing the oxygen partial pressure in the chamber, the positive and negative bias stress values improve to +0.32 V and −2.08 V, respectively. X-ray photoelectron spectroscopy is performed to reveal the cause of these improvements.

Drain Current Drop in Oxide Semiconductor Thin-Film Transistors: The Mechanisms and a Solution

The reliability of amorphous oxide semiconductor thin-film transistors (AOS-TFTs) is vital for high-definition displays and functional electronic devices. However, drain current drop (DCD) degradation has been commonly observed in the output characteristics of thin-film transistors (TFTs) with channel lengths of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L} &lt; 10 \mu \text{m}$ </tex-math></inline-formula> . Here, we show that DCD is a reversible process that is closely related to reduced metal-oxygen bonds. Based on device theory and simulations, we propose that the DCD effect is mainly caused by hot carriers, whose velocities are inversely proportional to the drain depletion width. Therefore, DCD failure could be alleviated simply by using the drain-offset structure. Experiments show that drain-offset TFTs improve DCD critical voltages (by ~130%) without sacrificing the ON-/ OFF-ratio. These studies provide theoretical and experimental approaches to effectively suppress DCD.

Mechanism of Non-Ideal Transfer Characteristic at Low Drain Voltage in Metal-Capped Amorphous Oxide Thin Film Transistor

Issues of amorphous oxide semiconductors (AOSs) thin-film transistors (TFTs) mainly focus on improving electrical performance and stability. Currently, the hump, the abnormal transfer characteristic, is also an essential factor of AOSs TFT. The hump phenomenon was observed for AOS-TFTs with a metal capping (MC) layer under various measurement conditions. The mobility in the MC TFT was improved from 14.8 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs to 19.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs compared to that of the conventional TFTs. The improved electrical characteristics in the MC structure are representative of the carrier injection effect and the change of the current path. This reason reveals that the MC structure has a hump phenomenon under the low drain to source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{DS}$ </tex-math></inline-formula> ). The hump characteristic does not significantly affect the overall MC TFT characteristics (transfer characteristic, improved electrical characteristics through MC structure, etc.). In addition, it was confirmed that it exhibits very stable hump characteristics through repeated measurements and uniformity. It was found that two current paths are formed mainly due to carrier injection from the metal capping layer in the hump phenomenon observed at low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{DS}$ </tex-math></inline-formula> . These divided current paths can lead to two on-currents ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> ) in the transfer curve. Many studies have recently been conducted to fabricate semiconductor devices with multi-values such as 0, 1, and 2. This divided current path could propose a simple method to achieve multi-values with an easy process.