AM-PM Distortion Research Articles

Nonlinear Capacitance Compensation Method for Integrating a Metal–Semiconductor–Metal Varactor with a Gallium Nitride High Electron Mobility Transistor Power Amplifier

A nonlinear capacitance compensation technique is presented in this paper to enhance the linearity of a power amplifier (PA) in the GaN process. The method involves placing an MSM varactor device alongside the GaN HEMT device, which works as the amplifying unit such that the overall capacitance observed at the amplifier input is constant, thus improving linearity. This approach is a reliable and straightforward way to improve PA linearity in the GaN process. The proof-of-concept prototype in this study involves the fabrication of a PA device using a standard GaN HEMT process, which successfully integrates the proposed compensation technique and demonstrates excellent compatibility with existing processes. The prototype has a saturation output power of 18 dBm, a peak power-added efficiency of 51.8%, and a small signal gain of 15.5 dB at 1 GHz. The measured AM–PM distortion at the 5 dB compression point is reduced by more than 50% compared to that of an uncompensated device. Furthermore, the results of third-order intermodulation distortion demonstrate the effectiveness of the linearity enhancement concept, with values improved by more than 5 dB in the linear region compared to those of the uncompensated device. All of the results demonstrate the potential utility of this design approach for wireless communication applications.

A Digital IR-UWB Transmitter With High Spectrum Utilization and AM-PM Distortion Calibra

A Digital IR-UWB Transmitter With High Spectrum Utilization and AM-PM Distortion Calibra

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications

An efficiency-enhanced fully integrated power amplifier (PA) for wireless local area networks (WLANs) was implemented based on the GaAs heterojunction bipolar transistor (HBT) process. A harmonic tuning network that can absorb the parasitic inductance of the bonding wires is proposed, which reduces the chip area significantly. The network provides nearly optimum fundamental and second harmonic impedances from 5.0 to 5.5 GHz. Additionally, a novel adaptive bias circuit that corrects the AM-AM and AM-PM distortion and improve thermal stability at high input power was proposed. With a chip dimension of only 1.06 mm2, the PA achieves a gain of 31.1-31.6 dB and saturated power of 29.9-30.3 dBm with a peak power-added efficiency (PAE) of 49.3%-51.8% across 5.0-5.5 GHz. The PA also shows an output power of 22.1 dBm (EVM=-32 dB) with 18.4% PAE under an 802.11ac MCS9 VHT160 test signal. In addition, the PA delivers 17.5 dBm (EVM=-42 dB) output power when tested with the 802.11ax MCS11 VHT160 signal at 5.25 GHz.

공통 소스 트랜지스터의 Self-Body-Biasing을 통해 선형성이 향상된 2.45 GHz CMOS 전력증폭기의 설계

This study introduces the design of an RF CMOS power amplifier based on a cascode powercell. self-body-biasing (SBB) of common source (CS) transistors (TRs) was proposed to improve the nonlinearity of power amplifiers. Accordingly, an analysis of the linearization principle of SBB was performed through simulation. The SBB technique is configured by inserting a 4 kΩ resistor between the body and the drain of the CS TRs. Accordingly, using the SBB to the CS TRs could achieve the effect of reducing the third-order intermodulation distortions (IMD3) by changing the third-order transconductance (gm3). Moreover, an effect of reducing AM-PM distortions could be achieved by securing a voltage condition in which the CG TRs could operate in a saturation region, which reduces the variation of parasitic capacitances at the output terminal.

A 54–68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS

This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54—68 GHz frequency band while consuming only 110 mW.

Load Modulated Balanced Amplifier Design Method Based on Complex Impedance Trajectories

This paper presents a design methodology for a load modulated balanced amplifier (LMBA) focusing on AMPM distortion mitigation. By introducing second harmonic control as a degree of design freedom, a complex load trajectory can be selected to compensate for AMPM nonlinearities in the device without substantially affecting efficiency. A mathematical derivation is accompanied by a design procedure based on closed-form equations to fabricate an LMBA based solely on load-pull data. The theory is validated through the measured comparison of three different designs operating at 2.4 GHz in a pseudo-RF-input Doherty-like LMBA configuration, with class-J, -B, and -J* main PAs. The class-J prototype outperforms the other designs with 54% and 49% drain efficiency at peak output power and 6-dB back-off, respectively, and only 4 degrees of AM-PM across this power range. When driven with a 10-MHz, 8.6-dB PAPR LTE signal, 40.5% average efficiency is achieved with better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-40.5$</tex-math></inline-formula> dBc ACLR without digital predistortion.

A 50–82 GHz broadband cascode-based power amplifier in 40 nm CMOS

In this paper, we present a broadband two-stage cascode-based power amplifier (PA) in 40 nm CMOS technology that covers the ISM band applications at 60 GHz, E-band applications channels (71–76 GHz, 77 GHz, 81–86 GHz), and Automotive radar application at 77 GHz. The bypass capacitor at the gate of the upper transistor of the cascode, which controls the swing, stability, and gain compression significantly, is studied and optimized carefully. Furthermore, a holistic design approach is provided to further optimize the input, output and interstage wideband matching networks to simultaneously improve the output power and gain performance over the whole operating frequency band. The measurement results show a power gain of 13 ± 1.5 dB, a maximum power added efficiency (PAE) and output gain compression point (POut1dB) of 15% and 11 dBm, respectively, while consuming 130 mW. Additionally, the PA achieves low measured group delay variations of 20 ± 10 ps and small measured AM-PM distortion < 3 degrees over the whole band.

A Predistortion-Less Digital Transmitter With −50-dB ACLR Exploiting Output Conductance Linearization

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of −50 dB and an error vector magnitude (EVM) of −45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

A 42–62 GHz Transformer-Based Broadband mm-Wave InP PA With Second-Harmonic Waveform Engineering and Enhanced Linearity

Indium phosphide (InP) heterojunction bipolar transistors (HBTs) with $f_{t}/f_{\max}$ of 350/675 GHz are studied and explored for a linear, high efficiency and broadband power amplifiers (PAs) at mm-wave frequencies. Unlike the conventional transmission-like-based design, this article presents a compact, broadband transformer-based power combining and impedance matching using the waveform engineering approach. We present, for the first time, mm-wave (40–60 GHz) InP topologies incorporating the following: 1) on-chip transformer for broadband, efficient and compact impedance matching and power combining; 2) synthesis of optimal second-harmonic impedance through transformer center tap to achieve high-efficiency differential PA operation; and 3) biasing techniques to reduce AM–PM distortion for linearity enhancement. This work reports a transformer-based push–pull InP PA in $0.25~\mu \text{m}$ technology across 42–62 GHz demonstrating a peak power added efficiency (PAE) of 39.5% and peak $P_{\text{sat}}$ of 20.6 dBm. The PA supports 4 GHz bandwidth at 52 GHz with an EVM of −22.9 dB and an adjacent channel leakage ratio (ACLR) of −32 dBc for an 8 Gb/s QPSK signal at 13.3 dBm average output power. This work presents one of the highest efficiency with wide bandwidth and highest linearity mm-wave PAs in integrated technology.

A Highly Linear and Efficient 28-GHz PA With a P sat of 23.2 dBm, P 1 dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS

This article presents a 28-GHz power amplifier (PA) suitable for fifth-generation (5G) wireless systems. Designed in a 65-nm bulk CMOS, the PA achieves a saturated output power ( $P_{\text {sat}}$ ) of 23.2 dBm at 28 GHz. The AM–AM and the AM–PM distortion have the overshoot of less than 0.3 dB and 0.2°, respectively, at 28 GHz. The AM–PM variation remains less than 1.9° over the frequency band of 26–31 GHz with a peak power-added efficiency (PAE) of 35.5%. Several techniques, including strategic placement of varactors, a proposed multi-function coplanar-waveguide (CPW)-like power combining structure, and a systematic design approach for the passive networks, are used to improve the efficiency and linearity of the design leading to a negligible difference between $P_{1\,\text {dB}}$ and $P_{\text {sat}}$ . The proposed linearity improvement technique, which uses an adaptive feedback structure to adjust the input impedance of the output stage based on the output power and also direct more current at higher output power levels, enhances the linearity through lowering both AM–AM and AM–PM conversions. The design enables 2.5-GS/s 64-QAM operation at average $P_{\text {out}}$ of 16.1 dBm with an error-vector magnitude/adjacent-channel power ratio (EVM/ACPR) of better than −26.2-dB/−28.32-dBc without using any digital pre-distortion.

Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI

A pseudo-differential distributed power amplifier (DPA) based on complementary gain stages is presented for wideband femtocell 5G indoor communications in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. Capacitive equalization is used to achieve flat bandwidth over the desired frequency range. Due to the complementary gain stages, no expensive bias-Ts are required. In order to improve reverse isolation and increase the output power, stacking is utilized. The design uses back-biasing to set the drain voltages of the DPA instead of the sensitive gate biases. The differences in the design process between a distributed amplifier (DA) and a DPA are presented. Tradeoffs between gain–bandwidth (GBW), reliability, peak power-added efficiency (PAE), output power, and amplitude-to-phase (AMPM) linearity are explored. The DPA achieves an 11.6-dB gain, a 0.4–31.6 GHz 3-dB small-signal bandwidth, and a 16.4 dBm peak-saturated output power ( $P_{\text {SAT}}$ ) with a 17.2% PAE from the 2.5-V supply. AMPM distortion at output-referred 1-dB compression point (OP 1 dB) and at $P_{\text {SAT}}$ is less than 2°/5° up to the 31 GHz, respectively. It achieves 10 dBm average output power reaching 80/96 gigabit per second (Gbit/s) at 17 GHz with 16/64 QAM modulation. At 28 GHz, it achieves 6.4/4.5 dBm output power with 12/8-Gbit/s data rate with 64/256 QAM modulation.

Injection Locking in Switching Power Amplifiers

In this work, injection locking in switching power amplifiers (PAs) is studied. Traditionally, injection-locked PAs (ILPAs) have supported phase modulation, with injection locking used primarily to improve the power-added efficiency by reducing the power required to drive the ILPA. Since the output power in conventional ILPA architectures is mainly contributed by the locked oscillator in an ILPA, the amplitude modulation is difficult to achieve unless supply modulation is employed. In the ILPA presented in this work, it is shown that by injection locking a switching PA and a power oscillator, improvement in both power-added efficiency and drain efficiency can be achieved as compared to just a switching PA. Moreover, amplitude modulation at a fixed supply voltage is achieved using an RF-DAC approach to scale both the switching PA and the locked oscillator. This approach employs variable injection-strengths varying from ≤1 (weak injection locking) to >1 (strong injection locking) to achieve the required power back-off. Accordingly, new formulations are introduced to extend the existing injection locking theory for injection strengths >1 case in ILPAs. Benefits of a larger injection strength on lock-range, maximum allowable symbol rate, AM-PM distortion and phase noise performance for an ILPA is provided. An ILPA is designed to support 64-QAM and implemented in a standard 65-nm bulk CMOS process. A peak drain efficiency of 42.7% and power-added efficiency of 40% is measured at the highest output power of 23 dBm, operating from a 1.45 V PA power supply at 2.5 GHz. Modulation tests with 5/50 MSym/s 64-QAM signals achieve the measured RMS EVM of 1.9%/3.1% with the average output power, drain efficiency and power-added efficiency of 18.1 dBm, 27.9% and 25.8% at 2.5 GHz, respectively.

Millimeter Wave SOI-CMOS Power Amplifier With Enhanced AM-PM Characteristic

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation

This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with builtin large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear phase compensation. To the best of our knowledge, it is the first time the amplitude modulation (AM)-phase modulation (PM) response in V-DPA is explained in detail. The PA exploits the lagging AM-PM distortion of C-DPA and leading AM-PM distortion of V-DPAs, resulting in built-in large-signal phase nonlinearity cancellation without phase pre-distortion. Moreover, the transformer-based Doherty output network provides active load modulation to both C-DPA and V-DPA, achieving a three-way Doherty PA for deep power back-off (PBO) efficiency enhancement without supply modulation. Finally, the 1.2-V single power supply for PA power cells and input drivers reduces supply complexity. As a proof-of-concept, the hybrid three-way digital Doherty PA is implemented in a 45-nm CMOS SOI process. The measurements show a 38.5% peak drain efficiency (DE), 22.4-dBm saturated output power (Psat), and 32.1%/18.7% DE at 3.4-/9.3-dB PBO, achieving ×1.25/×1.46 PBO efficiency enhancement over idealistic class-B PA PBO efficiency at 2.3 GHz. The measured AM-PM distortion is 4.7° which is state-of-the-art among DPAs with PBO efficiency enhancement. The hybrid digital Doherty PA supports 40-/10-MSym/s 64-quadrature amplitude modulation (QAM)/256-QAM at 15.3-/15.2-dBm average output power and 24.7%/23.2% average PA DE while maintaining error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) lower than -32/-32.1 dB and -30.6/-28.9 dBc without phase pre-distortion.

Linearity Improved Doherty Power Amplifier Using Non-Foster Circuits

In this paper, linearity improved Doherty power amplifier (DPA) is proposed for linearity improvement by modifying the input capacitor value of peaking amplifier. The non-foster circuits are substituted for the conventional λ/4 transmission line in front of peaking amplifier, which the 90° phase shifter and impedance matching can be performed by the proposed structure. Furthermore, the input capacitor value of peaking amplifier FET can be modified through modifying bias voltage and match resistance of non-foster circuits. Therefore, the AM-PM distortion of peak amplifier is suppressed, and the linearity of total DPA is improved. Compared to a conventional DPA, the third-order inter-modulation distortion of proposed DPA is reduced by 12 dB without cutting efficiency.

Class-J SiGe &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$X$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band Power Amplifier Using a Ladder Filter-Based AM–PM Distortion Reduction Technique

In this paper, a class-J power amplifier for operation in the X-band realized in SiGe bipolar technology is presented. The proposed design combines the high efficiency of class-J operation with solutions to mitigate AM-PM distortion down to a level compatible with high spectral efficiency modulation schemes like 64-QAM. The design of a transformer-based output matching network and the trade-off between efficiency and pure class-J operation related to a non-ideal second harmonic termination are discussed. The main sources of AM-PM distortion are identified in the base-emitter and collector-based bipolar junction transistor capacitance variation with power level and solutions that make the design less sensitive to these impairments are proposed. Linear MIM capacitors are used at the power amplifier (PA) core output to realize the proper class-J second harmonic termination, while an input matching network based on a Bessel ladder filter is adopted to make the signal phase at the PA core input less sensitive to base-emitter capacitance variation. A class-J PA previously designed for maximum power-added efficiency (PAE) is used as a reference throughout the paper to highlight the trade-off’s entailed by AM-PM distortion reduction. The designed PA features a peak gain of 15 dB at 10 GHz and 8-to-12 GHz −3 dB bandwidth. The saturated power is 22 dBm with a 33% PAE, while the output $p_{1\,\text {dB}}$ is 19 dBm. The AM-PM distortion at $p_{1\,\text {dB}}$ is 5 degrees.

A methodology for designing class-F−1/J(J−1) high efficiency concurrent dual-band power amplifier

This paper, presents a methodology for designing concurrent dual-band power amplifier (DB-PA) that operates in Class-F−1 at one band and Class-J or Class-J−1 at the other band. It is shown that the second harmonic engineering of Class-F−1 and Class-J or Class-J−1 makes these classes of operation compatible in terms of dual-band realization without introducing higher complexity in realizing the harmonic control network. The design methodology is well illustrated and is validated by implementing a Class F−1/J concurrent dual-band PA operating at 1842 and 2655 MHz bands. Experimental results exhibit output powers of 40 and 41 dBm and efficiencies of 76% and 70% at the lower and upper bands, respectively. The AM-AM, AM-PM and two-tone third-order inter-modulation distortion results imply a good linearity behaviour of the designed PA. Furthermore, the linearity of the designed DB-PA is also verified with a single carrier WCDMA signal, where the PA shows better than −20 dBc adjacent channel power ratio in saturation region at both of the operating bands.

Highly linear combining CMOS PA with AAAC

A highly linear and efficient CMOS power amplifier (PA) with adaptive auxiliary amplifier control (AAAC) is presented, which makes the common-gate transistor of an auxiliary amplifier operate in the saturation region for overall output powers. This leads to decrease the AM–PM distortion by reducing the variation of the output susceptance. In addition, the AAAC reduces the current consumption for all power ranges by controlling the auxiliary amplifier. The PA is fully integrated with all matching networks in a 0.18 μm CMOS process. It was measured with an 802.11n 64-QAM MCS7 signal. It achieved a maximum average power of 19.9 dBm with a power-added efficiency of 28% under an error-vector magnitude of −25 dB.

A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM–PM Distortion Self-Compensation

This paper presents a fully integrated wideband current-mode digital polar power amplifier (DPA) in CMOS with built-in AM–PM distortion self-compensation. Feedforward capacitors are implemented in each differential cascode digital power cell. These feedforward capacitors operate together with a proposed DPA biasing scheme to minimize the DPA output device capacitance $C_{d}$ variations over a wide output power range and a wide carrier frequency bandwidth, resulting in DPA AM–PM distortion reduction. A three-coil transformer-based DPA output passive network is implemented within a single transformer footprint (330 $\mu \text{m} \,\, \times $ 330 $\mu \text{m}$ ) and provides parallel power combining and load impedance transformation with a low loss, an octave bandwidth, and a large impedance transformation ratio. Moreover, this proposed power amplifier (PA) output passive network shows a desensitized phase response to $C_{d}$ variations and further suppresses the DPA AM–PM distortion. Both proposed AM–PM distortion self-compensation techniques are effective for a large carrier frequency range and a wide modulation bandwidth, and are independent of the DPA AM control codes. This results in a superior inherent DPA phase linearity and reduces or even eliminates the need for phase pre-distortion, which dramatically simplifies the DPA pre-distortion computations. As a proof-of-concept, a 2–4.3 GHz wideband DPA is implemented in a standard 28-nm bulk CMOS process. Operating with a low supply voltage of 1.4 V for enhanced reliability, the DPA demonstrates ±0.5 dB PA output power bandwidth from 2 to 4.3 GHz with +24.9 dBm peak output power at 3.1 GHz. The measured peak PA drain efficiency is 42.7% at 2.5 GHz and is more than 27% from 2 to 4.3 GHz. The measured PA AM–PM distortion is within 6.8° at 2.8 GHz over the PA output power dynamic range of 25 dB, achieving the lowest AM–PM distortion among recently reported current-mode DPAs in the same frequency range. Without any phase pre-distortion, modulation measurements with a 20-MHz 802.11n standard compliant signal demonstrate 2.95% rms error vector magnitude, −33.5 dBc adjacent channel leakage ratio, 15.6% PA drain efficiency, and +14.6 dBm PA average output power at 2.8 GHz.