Altera DE2 Research Articles

FPGA in hardware description language based digital clock alarm system with 24-hr format

Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.

An Efficient EEG Signal Analysis for Emotion Recognition Using FPGA

Electroencephalography (EEG), electromyography (EMG), galvanic skin response (GSR), and electrocardiogram (ECG) are among the techniques developed for collecting psychophysiological data from humans. This study presents a feature extraction technique for identifying emotions in EEG-based data from the human brain. Independent component analysis (ICA) was employed to eliminate artifacts from the raw brain signals before applying signal extraction to a convolutional neural network (CNN) for emotion identification. These features were then learned by the proposed CNN-LSTM (long short-term memory) algorithm, which includes a ResNet-152 classifier. The CNN-LSTM with ResNet-152 algorithm was used for the accurate detection and analysis of human emotional data. The SEED V dataset was employed for data collection in this study, and the implementation was carried out using an Altera DE2 FPGA development board, demonstrating improved performance in terms of FPGA speed and area optimization.

Design and Implementation of Multi Player Pong Game using Altera DE2 Board

Pong game is a simple but entertaining game of logic control. This research paper presents the design and implementation of an FPGA-based Pong game that runs on an Altera DE2 board using Verilog HDL. This article explains the VGA controller, object creation and animation, and text subsystem and of course how to link them all together to build a functioning circuit. There is an interesting multi-player mode and single-player mode feature in this design scheme. This game's multiplayer mode features both real-time and automatic players to create a competitive atmosphere. This design method followed less complicated, fastest processing, and utilized memory requirements and logic elements. The single-player mode uses 1.3% of total logic elements, the two-player mode uses 1.32%, and automatic player vs. real player uses 1.456% of total logic elements which is very small compared to the other gaming schemes and it reduces the processing time that is cost-effective for universal use. All the modules are designed by using Verilog HDL. The synthesis is done with the help of Altera DE2 FPGA. Functional simulation and synthesis prove that the design is universally usable and combines different modules in one module that presents sound entertainment and extends the electronics application-based work in the future.

Design and Implementation of a Multiplier free FPGA based OFDM Transmitter

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of the implemented blocks (VHDL code) and compare them with corresponding results from simulation system implemented in matlab 2010a. The results of these practical tests show that the suggested approach gives a significant improvement in reducing complexity and processing delays (45 nsec) in comparison with the conventional implementations of OFDM transmitter.

Design and Implementation of Communication Digital FIR Filter for Audio Signals on the FPGA Platform

Digital Signal Processing (DSP) in telecommunications is widely used for its outstanding performance. Hence, optimal results would be obtained with the sophisticated design and implementation of the digital Finite Impulse Response (FIR) filter. In this paper, the design and implementation of the FIR filter for processing the audio signal are obtained through the Field-Programmable Gate Array (FPGA) platform -Altera DE1 board. The design is divided into three primary blocks, which are the S2P Adapter block, Codec initialization block, as well as FIR filter block, which were then interfaced together; then, every block was compiled and simulated in order to obtain accurate results. The whole system was built to be functional, and finally, the frequency response was obtained. 100% significant accuracy and high quality are examined for implementing the filter in FPGA platform chip board programmed in (VHDL).

An FPGA application of home security code using verilog

Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

Design of a custom frequency divider for aviation equipment using the Kit FPGA Altera DE2

When operating aviation equipment or when working on test benches, test tables, etc., it is necessary to choose the right frequency to use. The custom frequency divider was designed by the author with the purpose of giving the right frequency to the desired frequency. A custom frequency divider was installed on Kit Altera DE2. The frequency selection is set by the user via push buttons.

FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

Моделирование 16-QAM в среде MATLAB и его реализация на Altera DE2-115

Моделирование 16-QAM в среде MATLAB и его реализация на Altera DE2-115

FPGA Seven-Segment-Display by Using Altera DE2-115 Board with Practice and Implementation

This paper presents a simple implementation of Seven-Segment Displays in very simple way by using “Altera DE2-115 Board” to understand the idea for those students who are not in the field of Electrical and computer science field. Seven-Segment Displays are used to display input data on FPGA Device. The main focused of this paper is to implement and practice Seven-Segment Displays by using Verilog file in which we must write code in C++ and execution simulations on innumerable counter designs and implement designs on FPGA device utilizing Seven-Segment Displays and Switches. The control consumption and the delay of unit is predictable using the synthesizer “Quartus Prime” and get simulation result by using “ModelSim”.

A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme

As quantum computers become more affordable and commonplace, existing security systems that are based on classical cryptographic primitives, such as RSA and Elliptic Curve Cryptography ( ECC ), will no longer be secure. Hence, there has been interest in designing post-quantum cryptographic ( PQC ) schemes, such as those based on lattice-based cryptography ( LBC ). The potential of LBC schemes is evidenced by the number of such schemes passing the selection of NIST PQC Standardization Process Round-3. One such scheme is the Crystals-Dilithium signature scheme, which is based on the hard module-lattice problem. However, there is no efficient implementation of the Crystals-Dilithium signature scheme. Hence, in this article, we present a compact hardware architecture containing elaborate modular multiplication units using the Karatsuba algorithm along with smart generators of address sequence and twiddle factors for NTT, which can complete polynomial addition/multiplication with the parameter setting of Dilithium in a short clock period. Also, we propose a fast software/hardware co-design implementation on Field Programmable Gate Array ( FPGA ) for the Dilithium scheme with a tradeoff between speed and resource utilization. Our co-design implementation outperforms a pure C implementation on a Nios-II processor of the platform Altera DE2-115, in the sense that our implementation is 11.2 and 7.4 times faster for signature and verification, respectively. In addition, we also achieve approximately 51% and 31% speed improvement for signature and verification, in comparison to the pure C implementation on processor ARM Cortex-A9 of ZYNQ-7020 platform.

Comparison of PO and INC MPPT Methods Using FPGA In-The-Loop Under Different Radiation Conditions

The Maximum Power Point Tracking (MPPT) algorithms are applied to obtain maximum efficiency under different atmospheric conditions in photovoltaic (PV) systems. Perturb&Observe (PO) and Incremental Conductance (INC) methods are the oldest algorithms used among MPPT methods. Field Programmable Gate Arrays (FPGA) are used especially in applications requiring high speed. FPGA in-the-loop feature is used to test algorithms designed in MATLAB/Simulink environment. In this study, PO and INC methods have been designed to work in FPGA environment. Both algorithms have been tested under different radiation conditions using FPGA-in-the-loop feature. The FPGA in-the-loop simulation result of PO and INC methods has been graphically shown. In this study, Altera DE2-115 development board was used to test PO and INC MPPT algorithms. On the other hand, PO and INC methods were synthesized using the Quartus-II program. Comparisons of simplicity of algorithms were made according to synthesis results. Thus, by using the FGPA in-the-loop feature and performing the synthesis process, both the algorithms were tested and the areas covered by the algorithms in the FPGA were compared.

FPGA in-the-loop implementation of direct torque control for induction motor

In this study, the hysteresis based direct torque control (DTC) of a three-phase induction motor was carried out experimentally. The DTC algorithm was also modelled in the hardware environment by using FPGA’s in-the-loop feature. The dSPACE DS1103 controller board was used in the experimental study and Altera DE2-115 model development board was used in the hardware modelling. Both applications had the same sample time and all of the DTC algorithm was tested within the FPGA. The hardware simulation study conducted in FPGA environment was carried out in MATLAB/Simulink environment. The experimental results were compared with the hardware simulation results obtained from FPGA. As a result of the comparison, it was shown that DTC algorithm could be realized easily in FPGA environment without experimental installation, and the obtained current, voltage and velocity graphs were similar.

Моделирование приемника SDR в среде MATLAB и его реализация на Altera DE2-115

Моделирование приемника SDR в среде MATLAB и его реализация на Altera DE2-115

NMR configurations with novel majority voter circuits to mask multiple module faults

Mission, safety, and business-critical applications need uninterrupted operation with correct results. But due to the technology shrinking, the microelectronic circuits can be affected by many faults like permanent, transient, and intermittent. So, there is a considerable demand for designing fault-tolerant systems. Hardware redundancy configurations have been widely used to protect or mask faults. In this research article, to mask multiple faults, N-modular redundancy (NMR) configurations are deployed, namely 5-MR and 7-MR configurations, which are implemented to mask two and three function module errors. Two majority voter (MV) circuits with 5-MR and 7-MR have been proposed, respectively. Simulation results are obtained with Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). With ASIC, 120 nm technology is used with BSIM4 Spice simulation parameters. Also, the majority voters are evaluated with a band-pass filter as the function module on Altera DE2-115 FPGA using the Quartus II synthesis tool. The very high-speed integrated circuits hardware description language is used with FPGA implementation. Simulation results reveal that the proposed MV circuits obtain better results than the existing methods.

Real Time Detection of Object Blob Localization Application using 1-D Connected Pixel and Windowing Method on FPGA

Blob detection and localization is a common process used in the machine vision. Current existing blob detection method is using 2-dimensional kernel matrix which is higher in time consumption and also memory space. This study has proposed a dedicated digital architecture consist of two modules to detect binary image blob using only 1 -dimensional image pixel. First module is used to detect connected pixel in a row of pixel, and second module is used to perform windowing to justify blob location. This study has been successfully implemented and tested on Altera DE2 FPGA board. The proposed architecture only takes 24 clock cycles to deliver blob location and related features. The tested architecture only utilizes 1597 logic element, or 4.81% of the FPGA total resources.

Position and speed optimization of servo motor control through FPGA

We have put our model in this paper in which we will be controlling the speed and direction of the servomotor through FPGA. So, as to guarantee the precision from the check control procedure, we have made a project in which the document provides the control plane associated with servo motor depending on Altera DE1 board gentle primary processor as program controller. The system utilizes FPGA since the primary gadget, as well as within Quartus II 10.0 program atmosphere. The associated control components aremade to type a good executable control program in which speed and direction will be controlled the servo motor performance. The particular handle signs from your handle method are usually separated and amplified which results in the push to appreciate the particular handle with the servo motor. Based on the features associated with Altera, it is expounded through 2 facets of equipment’s hardware as well as a software program that supplies an answer for that style associated with the servo control system. This particular document utilizes the actual PID control formula to manage the actual common screening device to attain versatile as well as precise control reasons. The actual equipment execution from the PID control formula is put in place through FPGA; precise as well as effective control program is built to enhance the speed and performance of the servomotor through FPGA.

FPGA-based Fast Algorithm of Correcting Saturated Pixel in Image

This paper proposes a novel method to correct saturated pixels in images. This method is based on the YCbCr color space and separately corrects the chrominance and the luminance of saturated pixels. In this algorithm, the saturated image is processed on the scan line, which is beneficial to the hardware implementation and the correction effect is good. Through the results of the joint simulation of MATLAB and Modelsim, it can be concluded that the hardware algorithm of this paper can use less resources to achieve fast correction. This paper uses Altera DE4 high-level development platform for hardware implementation. The calculation results show that highspeed image and video processing by FPGA is feasible and efficient, and it can be done frame by frame for highdefinition video. It has broad practical application prospects.

Character Recognition By Implementing FPGA-Based Artificial Neural Network

A non-linear applied math knowledge modelling tool, Artificial Neural Networks (ANN) are predominantly used to model complicated interactions between inputs and outputs or to look for patterns within the data. Using VHDL coding, we developed a generic hardware-based ANN. This classifier has been trained to recognize letters on a 4x4 binary grid that a user fills out using 16 toggle switches. An LCD shows the most likely classification that the ANN proposed. The ANN was taught to recognize 20 English character patterns and 9 Arabic character patterns on a 4x4 grid to showcase the viability of the FPGA execution of ANN. The Altera DE2 development and education board use the generated design file to flash the Altera Cyclone II FPGA. A training supervisor is also included in the design, which is responsible for training the ANN to recognize a set of 29 standard characters drawn from the English and Arabic alphabets. Positive patterns were found, with the ANN successfully recognizing all training characters. Finally, this study demonstrates the adaptability and boundless possibility of hardware-based implementation of ANN and the infinite possibility of prototyping and building recent systems with VHDL coding on an FPGA platform.

Design and implementation of HDL remote controller for smart home system

<span>This work presents a design and development of a remote controller application using an Altera DE2-115 board. A remote controller lighting provides smart technologies make it viable to monitor, control and support users in which can enhance the quality life and promote independent living. Nowadays, to turn on the electrical devices, a user will go to the located switch. It is difficult and required more time to switch on the devices instead of staying at certain location while controlling the switching mode of the devices. Implementing this system, users do not need to have numerous switches in their home to turn on the lights as they can do this digitally from a switchless control located in one place or using a remote controller. The Altera board is built with eighteen slide switches which act as inputs and at the same time it will display the outputs on seven segments, LEDs and LCD display character. As a conclusion, the remote controller lighting system provides convenience and energy efficiency in order to allow the users to control the lighting system using smart devices. </span>