Altera DE2 Research Articles

VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

Composite Field Multiplier based on Look-Up Table for Elliptic Curve Cryptography Implementation

Implementing a secure cryptosystem requires operations involving hundreds of bits. One of the most recommended algorithm is Elliptic Curve Cryptography (ECC). The complexity of elliptic curve algorithms and parameters with hundreds of bits requires specific design and implementation strategy. The design architecture must be customized according to security requirement, available resources and parameter choices. In this work we propose the use of composite field to implement finite field multiplication for ECC implementation. We use 299-bit keylength represented in GF((2 13 ) 23 ) instead of in GF(2 299 ). Composite field multiplier can be implemented using different multiplier for ground-field and for extension field. In this paper, LUT is used for multiplication in the ground-field and classic multiplieris used for the extension field multiplication. A generic architecture for the multiplier is presented. Implementation is done with VHDL with the target device Altera DE2. The work in this paper uses the simplest algorithm to confirm the idea that by dividing field into composite, use different multiplier for base and extension field would give better trade-off for time and area. This work will be the beginning of our more advanced further research that implements composite-field using Mastrovito Hybrid, KOA and LUT.

Augmenting Computer Architecture Classroom Experience with FPGAs Based Learning

Computer architecture is often taught by using software to design and simulate hardware modules and then using individual components to implement them. Our aim in this paper is to share our teaching experience of this subject in a way to enhance student learning outcome by developing projects for the computer architecture lab to help students better understand the theoretical concepts of the subject and to gain hands-on type of experience and apply that for more realistic projects. As a result, we have noticed that students show better interest in learning and understanding the subject materials over the last few semesters. We present in this work an ALU computer module design exercise as we used it in our computer architecture course. This approach can be well adopted for a first course in digital logic design, computer organization, and/or computer architecture. In specific, we designed and implemented an 8-bit arithmetic and logic unit, which performs 14 different arithmetic and logic operations. We did the design, simulation, and FPGA-based implementation of the proposed ALU module using QUARTUS II design software and Altera DE2 FPGA Board.

Hardware Implementation of RFID Mutual Authentication Protocol

Radio-frequency identification (RFID) is a wireless technology that utilizes radio communication to identify objects with a unique electrical identity. The widespread deployment of RFID technologies may generate new threats to security and user privacy. One of the main drawbacks of RFID technology is the weak authentication systems between a reader and a tag. In general, ¿weak¿ authentication systems that either leak the password directly over the network or leak sufficient information while performing authentication allow intruders to deduce or guess the password. In this paper, we study the RFID tag-reader mutual authentication scheme. A hardware implementation of the mutual authentication protocol for the RFID system is proposed. The proposed system was simulated using Modelsim XE II and synthesized using Xilinx synthesis technology. The system has been successfully implemented in hardware using an Altera DE2 board that included an Altera Cyclone II field-programmable gate array (FPGA). Finally, the output waveforms from the FPGA were displayed on the 16702A logic analysis system for real-time verification.