ALICE Silicon Pixel Detector Research Articles

Operational experience with the ALICE Pixel Detector

The ALICE Silicon Pixel Detector (SPD) constitutes the innermost detector of the ALICE experiment, which is the LHC experiment dedicated to the investigation of strongly interacting matter in heavy-ion collisions.The SPD consists of ∼ 10 million pixels organized in two layers at radii of 39 mm and 76 mm that cover a pseudorapidity range of | η | < 2 and | η | < 1.4, respectively. It provides the position of the primary and secondary vertices, and it has the unique feature of generating a trigger signal that contributes to the L0 trigger of the ALICE experiment. Installed in 2007, the SPD started to record data since the first LHC collisions. This contribution presents the main features of the SPD, the detector performance and the operational experience, including calibration and optimization activities, since installation in ALICE. The ongoing consolidation activities carried out to prepare the detector for the data taking during the RUN2 of LHC will be also described.

Study of a trigger in p-p events for the HMPID detector in the ALICE experiment at LHC

The ALICE-HMPID detector extends the PID capabilities in the central rapidity region of the ALICE central detectors (ITS, TPC, TOF), by identifying charged pions and kaons with momentum 1 < p < 3 GeV/c and protons 1.5 < p < 5 GeV/c . Because of the small geometrical acceptance of HMPID, an efficient trigger system could enrich the sample of good events for physics. In this work, a simulation study to select events by using the Fast-OR signal of the ALICE Silicon Pixel Detector (SPD) combined with the signal from the ALICE Time-Of-Flight detector will be presented.

Operation and performance of the ALICE silicon pixel detector with proton-proton beams

Abstract The ALICE Silicon Pixel Detector (SPD) forms the two innermost barrel layers of the ALICE inner tracking system (ITS) and is made of hybrid silicon pixel detectors. The cell size is 50 μ m × 425 μ m and the SPD contains a total of about 107 readout cells. The two layers are located at average radii of 3.9 and 7.6 cm from the interaction point. The total material-budget of the SPD per layer is 1.14% X0. In addition of being a pixel detector with a very low material-budget in the sensitive area, the SPD is also capable of providing a fast trigger signal to contribute to the L0 trigger decision. The SPD has been installed in the experiment in 2007. Commissioning of the system was carried out in the following year, followed by several experimental cosmic runs in 2008 and 2009. The SPD was also operational during LHC beam injection tests as well as during the first beam collisions at the end of 2009. Since then the SPD has shown to be a key element of the ALICE experiment in providing data and trigger information. This presentation will review the experience gained during the commissioning of the detector and summarize the performance during the cosmic runs, LHC injection tests and first collisions.

Trigger performance of the ALICE Silicon Pixel Detector

Abstract The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the ALICE Inner Tracking System (ITS). It consists of two-layer barrel of hybrid silicon pixel detectors. The SPD contains 1200 pixel readout chips and about 107 pixel cells. The unique feature of the SPD among the vertex detectors of LHC experiments is the prompt trigger capability, called Fast-Or, which allows it to contribute to the experimental first level trigger decision. The SPD data stream includes 1200 digital signals (Fast-Or) promptly asserted by each readout chip on the presence of at least one pixel hit in the matrix. The off-detector Pixel Trigger system elaborates in real time the 1200 Fast-Or signals continuously received from the detector in order to generate a pre-processed signal for the ALICE first level trigger. All the Fast-Or signals are written in the data and available for offline analysis. In this contribution it is presented the methodology used to evaluate the performance of the Fast-Or. The methods are entirely based on offline data analysis. Results are given for a sample of data of proton–proton collisions at s = 7 TeV .

The ALICE Silicon Pixel Detector: commissioning and performance optimization

This paper describes the tests and measurements made during the final commissioning with beams of the ALICE Silicon Pixel Detector (SPD) in the first year of operation and the optimization of its performance.The ALICE Silicon Pixel Detector (SPD) is the innermost detector of the ALICE experiment and therefore plays a key role for vertexing and tracking. It consists of two cylindrical layers of pixel detectors, with a total of ∼ 107 pixels.The detector provides a prompt trigger signal that contributes to the first level trigger decision in ALICE. The trigger signal has been extensively used in the first trigger level of the ALICE experiment for recording data of proton-proton collisions at energies of 900 GeV, 2.36 TeV and 7 TeV.

Detector performance of the ALICE silicon pixel detector

The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the ALICE Inner Tracking System (ITS). It consists of two barrel layers of hybrid silicon pixel detectors at radii of 39 and 76 mm. The physics targets of the ALICE experiment require that the material budget of the SPD is kept within ≈ 1 % X 0 per layer. This has set some stringent constraints on the design and construction of the SPD. A unique feature of the ALICE SPD is that it is capable of providing a prompt trigger signal, called Fast-OR, which contributes to the L0 trigger decision. The pixel trigger system allows to apply a set of algorithms for the trigger selection, and its output is sent to the Central Trigger Processor (CTP). The detector has been installed in the experiment in summer 2007. During the first injection tests in June 2008 the SPD was able to record the very first sign of life of the LHC by registering secondary particles from the beam dumped upstream the ALICE experiment. In the following months the SPD has participated in the ALICE cosmic campaign to test the integration with all experimental sub-systems and to acquire data for alignment. Since the LHC start-up in November 2009, the SPD has been recording the LHC activities and in particular the first proton–proton collisions in ALICE.

The ALICE silicon pixel detector readout electronics

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracking system (ALICE Collaboration, 1999) [1]. The SPD is built with 120 detector modules (half-staves) and contains about 10 million pixels in total. The half-staves are connected to the off-detector electronics, housed in a control room 100 m away, via bidirectional optical links. The stream of data from the front-end electronics is processed in 20 VME readout modules, called routers, based on FPGAs. Three 2-channel link-receiver daughter cards, also based on FPGAs, are plugged in each router. Each link-receiver card receives data via the optical link from two half-staves, applies the zero suppression and passes them to the router to be processed and sent to the ALICE–DAQ system through the detector data link (DDL). The SPD control, configuration and data monitoring are performed using the VME interface embedded in the router.

The ALICE Silicon Pixel Detector

The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the ALICE inner tracker system. It contains 9.8×10 6 pixels with a material budget of less than 1% of X 0 per layer. It is based on hybrid pixel technology. The space and material budget constraints have severe impact on the design. The ALICE SPD detector system components are discussed.

The ALICE Silicon Pixel Detector control system and on-line calibration tools

The ALICE Silicon Pixel Detector (SPD) contains nearly107 hybrid pixel cells. The operation of the SPD requires on-linecontrol and monitoring of some 2000 parameters and ∼ 50000 DACs. Information for each channel is stored in aconfiguration database. Timing and data management ( ∼ 6 GB ofraw data for each calibration) are critical issues. An overview ofthe SPD electronics read out chain and of the detector controlsystem is given with a detailed description of the front-endcontrols and the calibration strategy. The status of commissioningand a preliminary evaluation of the detector performance arepresented.

The Level 0 Pixel Trigger system for the ALICE experiment

The ALICE Silicon Pixel Detector contains 1200 readout chips.Fast-OR signals indicate the presence of at least one hit in the8192 pixel matrix of each chip. The 1200 bits are transmitted every100 ns on 120 data readout optical links using the G-Link protocol.The Pixel Trigger System extracts and processes them to deliver aninput signal to the Level 0 trigger processor targeting a latency of800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various triggeralgorithms.The system uses advanced 12-channel parallel optical fiber modulesoperating at 1310 nm as optical receivers and 12 deserializer chipsclosely packed in small area receiver boards.Alternative solutions with multi-channel G-Link deserializers implementeddirectly in programmable hardware devices were investigated.The design of the system and the progress of the ALICE Pixel Triggerproject are described in this paper.

Production and Integration of the ALICE Silicon Pixel Detector

The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the Inner Tracking System (ITS) of the ALICE experiment at LHC. The SPD is made of hybrid silicon pixel detectors with a total of 9.8 × 10 6 readout cells. Device packaging and design of the detector were constrained by a maximum allowed module height of 2 mm and an overall material budget limit of 1% X 0 per layer. The integration of the detector parts is currently carried out in order to allow installation in the experiment at the end of 2006. An overview of the production status of the individual components is presented as well as the integration activities.

The ALICE Silicon Pixel Detector: System, components and test procedures

The ALICE Silicon Pixel Detector consists of two barrel layers of hybrid silicon pixel detectors. In total 9.8 × 10 6 pixel cells with 50 μ m × 425 μ m will provide precision tracking information in the high multiplicity environment expected in heavy ion collisions. This paper gives an overview of the system, its components and the test procedures that have been developed.

The mechanics and cooling system of the ALICE silicon pixel detector

The design and production phases of an extremely light carbon fibre supporting structure for the silicon pixel detector of ALICE is presented together with the integrated evaporative cooling system. Considering the very demanding material budget specifications where, in total, the average material traversed by a particle hitting perpendicular to the SPD should correspond to about 2% of a radiation length, the material choice, the qualification criteria and the system performances are extensively described for the mechanical and cooling system components with a short description of the critical specification defined by the very complex mechanical integration constraints.

Overview and status of the ALICE silicon pixel detector

The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the Inner Tracking System (ITS) of the ALICE experiment at LHC. The SPD is made of hybrid silicon pixel detectors with a total of 9.8 × 10 6 readout cells. The total material budget per layer is limited to less than 1% X 0 . The space and material budget constraints had strict implications on the design of the detector and the device packaging. An overview of the individual components of the SPD is presented as well as the status of production.

The ALICE silicon pixel detector front-end and read-out electronics

The ALICE silicon pixel detector (SPD) comprises the two innermost barrel layers of the ALICE inner tracker system. The SPD includes 120 half staves each of which consists of a linear array of 10 ALICE pixel chips bump bonded to two silicon sensors. Each pixel chip contains 8192 active cells, so the total number of pixel cells in the SPD is ≈10 7. The tight material budget and the limitation in physical dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. An essential part of the half stave is a low-mass multi-layer flex that carries power, ground, and signals to the pixel chips. Each half stave is read out using a multi-chip module (MCM). The MCM contains three radiation hard ASICs and an 800 Mbit/s custom developed optical link for the data transfer between the detector and the control room. The detector components are less than 3 mm thick. The production of the half-staves and MCMs is currently under way. Test results as well as on overview of the integration of the on-detector electronics are presented.

Recent test results of the ALICE silicon pixel detector

The ALICE SPD (Silicon Pixel Detector) forms the two innermost layers of the Inner Tracking System (ITS) of the ALICE experiment at LHC. After several years of development the production of the modules is starting. The present article provides an overview of the different elements that will be used in the SPD with special emphasis given to testing of wafers and bump-bonded ladders.

Test beam performance of the ALICE silicon pixel detector

The ALICE Silicon Pixel Detector (SPD) will include 1200 bump-bonded readout chips produced in a commercial 0.25 μ CMOS process. Each chip has 8192 pixels of size 50 × 425 μ m 2 , which leads to about 10 million readout channels in the whole detector system. Test beam measurements were recently carried out at the CERN SPS using a positive proton/pion beam as well as a 158 A GeV/ c heavy ion beam (In) with a fixed Pb target. Analysis show good performance of the ALICE chip and assemblies in the positive beam as well as in the high multiplicity In beam. Preliminary results from data analysis show good performance of the SPD and fulfill the ALICE requirements.

Test beam performance of the ALICE silicon pixel detector

The ALICE Silicon Pixel Detector (SPD) will include 1200 bump-bonded readout chips produced in a commercial 0.25 μ CMOS process. Each chip has 8192 pixels of size 50 × 425 μ m 2 , which leads to about 10 million readout channels in the whole detector system. Test beam measurements were recently carried out at the CERN SPS using a positive proton/pion beam as well as a 158 A GeV/ c heavy ion beam (In) with a fixed Pb target. Analysis show good performance of the ALICE chip and assemblies in the positive beam as well as in the high multiplicity In beam. Preliminary results from data analysis show good performance of the SPD and fulfill the ALICE requirements.

The silicon pixel detector (SPD) for the ALICE experiment

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the inner tracking system (ITS). The basic building block of the SPD is the half-stave carrying two detector ladders. The half-stave is equipped with a multi-chip module (MCM) and an optical fibre link for control and readout. A 5-layer aluminium/polyimide bus ensures the distribution of power and signals on each half-stave. The half-staves are mounted on a light-weight carbon-fibre structure with an integrated evaporative cooling system. An overview of the SPD development and the current status of the construction are presented.

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μm×425 μm pixel cells in the 256×32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32×32 array of 400 μm×425 μm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology.