Hardware Algorithms Research Articles

Application of an embedded general-purpose computing platform to passive acoustic monitoring

JASCO Applied Sciences has developed a novel passive acoustic monitoring system, the OceanObserverTM, that has been fielded in undersea and surface AUVs as well as on buoys and sub-sea observatories. The hardware is based on the Zynq system-on-a-chip (SoC), which features a large field-programmable gate array (FPGA) and two ARM processing cores. The FPGA is used to implement real-time filtering for the analog-to-digital converters and a real-time detector for odontocete clicks. JASCO’s PAMlab JAVA software has been adapted to run in the ARM processors. This allows for the detector algorithms to be tested and proven using recorded data sets, and the deployment of algorithms in the real-time hardware using the same proven software baseline. The advantages of this approach for rapidly adapting generic hardware to diverse monitoring projects will be highlighted.

Efficient Resource Scheduling for Multipath Retransmission over Industrial WSAN Systems.

With recent adoption of Wireless Sensor-Actuator Networks (WSANs) in industrial automation, wireless control systems have emerged as a frontier of industrial networks. Hence, it has been shown that existing standards and researches concentrate on the reliability and real-time performance of WSANs. The multipath retransmission scheme with multiple channels is a key approach to guarantee the deterministic wireless communication. However, the efficiency of resource scheduling is seldom considered in applications with diverse data sampling rates. In this paper, we propose an efficient resources scheduling algorithm for multipath retransmission in WSANs. The objective of our algorithm is to improve efficiency and schedulability for the use of slot and channel resources. In detail, the proposed algorithm uses the approaches of CCA (clear channel assessment)-Embedded slot and Multiple sinks with Rate Monotonic scheme (CEM-RM) to decrease the number of collisions. We have simulated and implemented our algorithm in hardware and verified its performance in a real industrial environment. The achieved results show that the proposed algorithm significantly improves the schedulability without trading off reliability and real-time performance.

A proof of the Beierle–Kranz–Leander conjecture related to lightweight multiplication in $$\mathbb {F}_{2^n}$$

Lightweight cryptography is an important tool for building strong security solutions for pervasive devices with limited resources. Due to the stringent cost constraints inherent in extremely large applications, the efficient implementation of cryptographic hardware and software algorithms is of utmost importance to realize the vision of generalized computing. In CRYPTO 2016, Beierle, Kranz and Leander have considered lightweight multiplication in $$\mathbb {F}_{2^n}$$. Specifically, they have considered the fundamental question of optimizing finite field multiplications with one fixed element and investigated which field representation, that is which choice of basis, allows for an optimal implementation. They have left open a conjecture related to an XOR-count of two. Using the theory of linear algebra, we prove in the present paper that their conjecture is correct. Consequently, this proved conjecture can be used as a reference for further developing and implementing cryptography algorithms in lightweight devices.

Quantum optical neural networks

Physically motivated quantum algorithms for specific near-term quantum hardware will likely be the next frontier in quantum information science. Here, we show how many of the features of neural networks for machine learning can naturally be mapped into the quantum optical domain by introducing the quantum optical neural network (QONN). Through numerical simulation and analysis we train the QONN to perform a range of quantum information processing tasks, including newly developed protocols for quantum optical state compression, reinforcement learning, black-box quantum simulation, and one-way quantum repeaters. We consistently demonstrate that our system can generalize from only a small set of training data onto inputs for which it has not been trained. Our results indicate that QONNs are a powerful design tool for quantum optical systems and, leveraging advances in integrated quantum photonics, a promising architecture for next-generation quantum processors.

Low-Cost FPGA Hardware Implementation of Matrix Converter Switch Control

An idea for a hardware realization of a space vector modulation in the direct matrix converter is proposed in this brief. The method is oriented toward the implementation in a low-cost field programmable gate arrays (FPGAs). The traditional algorithms usually involve digital signal processors, which drive the large number of power transistors and “non-standard positions of control pulses” during the switching sequence. Thus, hardware implementations have become popular since particular operations are performed faster and more efficiently. This brief proposes a novel hardware algorithm for a matrix converter switch control. Contrary to the existing hardware methods, the presented technique does not require specialized modeling tools, nor advanced converters to achieve the hardware representation. Furthermore, the proposed solution permits concurrent computation of most operations. The method has been verified experimentally. The results of the hardware implementation in a low-cost FPGA are discussed.

Neuromorphic Hardware Learns to Learn.

Hyperparameters and learning algorithms for neuromorphic hardware are usually chosen by hand to suit a particular task. In contrast, networks of neurons in the brain were optimized through extensive evolutionary and developmental processes to work well on a range of computing and learning tasks. Occasionally this process has been emulated through genetic algorithms, but these require themselves hand-design of their details and tend to provide a limited range of improvements. We employ instead other powerful gradient-free optimization tools, such as cross-entropy methods and evolutionary strategies, in order to port the function of biological optimization processes to neuromorphic hardware. As an example, we show these optimization algorithms enable neuromorphic agents to learn very efficiently from rewards. In particular, meta-plasticity, i.e., the optimization of the learning rule which they use, substantially enhances reward-based learning capability of the hardware. In addition, we demonstrate for the first time Learning-to-Learn benefits from such hardware, in particular, the capability to extract abstract knowledge from prior learning experiences that speeds up the learning of new but related tasks. Learning-to-Learn is especially suited for accelerated neuromorphic hardware, since it makes it feasible to carry out the required very large number of network computations.

Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems.

SVM algorithm oriented for implementation in a low-cost Xilinx FPGA

The paper proposes an idea of hardware realization of a space vector modulation (SVM) and transistor commutation method in the direct matrix converter (MC). The presented technique is oriented to an implementation in a single, low-cost programmable logic device (namely, field programmable gate array, FPGA). The SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which drive the large number of power transistors (18 transistors and 18 independent PWM outputs) and “non-standard positions of control pulses” during the switching sequence. Therefore, hardware implementations are becoming popular since computed operations may be executed much faster and more efficiently due to the concurrent nature of the digital devices. In the paper a hardware algorithm of the SVM computation is proposed. Contrary to the existing hardware methods, the presented solution neither requires specialized modeling tools (such as Matlab/Simulink, ISE EDK), nor advanced converters to achieve the hardware representation. It is assumed that the system is prepared in a pure hardware description language (namely, Verilog). Furthermore, the proposed technique permits concurrent execution of most operations. The presented algorithm has been verified experimentally with the low-cost Xilinx FPGAs (in particular, the devices from Artix-7 family). The results of the physical implementation are presented and discussed.

An improved image mixed noise removal algorithm based on super-resolution algorithm and CNN

Based on the hardware and sensors of image acquisition, the noise in the image has been easily generated. In this paper, an improved method of image decompression has proposed the shortcoming of the above-mentioned hardware algorithm. The traditional filter desiccation algorithm can only remove one or two specific noises, and it is not effective for other types. We combine some excellent neural network models. In this paper, an image mixing noise removal algorithm based on convolution nerve has been mentioned. Aiming at realizing the super-resolution of the image, the deconvolution layer can be used only to enlarge the image. The magnification factor is the step of deconvolution. This paper aims to eliminate the interference of the image noise. The effect of magnification on the deconvolution layer is impossible. The results of experimental test show that the algorithm achieves a good noise removal effect and is suitable for various mixed noise images. The algorithm used in this paper improves the subjective visual effect and objective evaluation index.

Test of a fast adaptive reclosing algorithm for transmission lines using a programmable hardware

This study presents the application of single-phase and three-phase adaptive reclosing method for transmission lines using a commercial protection relay. The method ensures the application of the automatic reclosing just after the extinction of a transient fault, the blocking of the automatic switching and, subsequently, the three-phase tripping for permanent faults. The study describes the proposed method implementation in a commercial relay. To represent both transient and permanent faults, oscillograms of real cases were used. The contributions of this work are the method to test the new algorithm in a commercial hardware, the distinction between transient and permanent faults and the detection of transient fault extinction through adaptive algorithms using commercial equipment.

Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification

Proportionate-type normalized LMS (Pt-NLMS) family of adaptive filtering algorithms for sparse system identification pose significant implementation challenges due to their high computational complexity especially for real-time applications like network echo cancelation. In this paper, we make the first attempt to implement Pt-NLMS algorithms in hardware. Several reformulations are proposed to simplify the original Pt-NLMS algorithms, thereby making them amenable to real-time VLSI implementations and the reformulated algorithms referred as delayed $\mu $ -law proportionate LMS (DMPLMS) algorithm for white input and delayed wavelet MPLMS (DWMPLMS) for colored input are then implemented in hardware. Simulation studies demonstrate that the performance loss is very small for the proposed reformulations. We implemented the proposed designs considering 16-bit fixed point representation in hardware, and synthesis results show that the DMPLMS architecture with ${\approx } 30\%$ increase in hardware over the state-of-the-art conventional delayed LMS architecture achieves $3\times $ improvement in convergence rate for white input and the DWMPLMS architecture with ${\approx } 70\%$ increase in hardware achieves $10\times $ improvement in convergence rate for correlated input conditions.

FPGA implementation of elephant recognition in infrared images to reduce the computational time

Object recognition is a challenging task in image processing and computer vision. In this paper, segmentation, feature extraction and classification methods are done for elephant recognition. Thresholding based segmentation technique is used for image segmentation and k-NN classifier is used for object recognition based on the shape features of the segmented image. Infrared elephant images are considered for experimentation. The database created by us for this type of object recognition includes elephant, bear, horse, pig, tiger, and cow and lion images. The recognition rate is calculated for performance evaluation. However, implementing such algorithms on software consumes more time as image sizes and bit depths grow larger. Hence this paper aims at hardware implementation of elephant recognition to reduce the computational time. The proposed hardware is prototyped inVirtex-4 xc4vlx25 FPGA using Xilinx System Generator (XSG) tool. The hardware/software co-simulation feature allows the input and output to be displayed on Matlab window while the processing is done through FPGA. The results indicate that when the category is elephant and if the recognition status is “yes”, recognition rate is 100%. If the category is not an elephant and if the recognition status is “no”, recognition rate is still 100% also indicates, the approach is successful in elephant recognition and the computation of segmentation algorithm and shape feature extraction (area, centroid, equivdiameter) in hardware reduces the computational time of elephant recognition by 89.65% as compared to software computation.

An On-Chip Trainable and the Clock-Less Spiking Neural Network With 1R Memristive Synapses.

Spiking neural networks (SNNs) are being explored in an attempt to mimic brain's capability to learn and recognize at low power. Crossbar architecture with highly scalable resistive RAM or RRAM array serving as synaptic weights and neuronal drivers in the periphery is an attractive option for the SNN. Recognition (akin to "reading" the synaptic weight) requires small amplitude bias applied across the RRAM to minimize conductance change. Learning (akin to "writing" or updating the synaptic weight) requires large amplitude bias pulses to produce a conductance change. The contradictory bias amplitude requirement to perform reading and writing simultaneously and asynchronously, akin to biology, is a major challenge. Solutions suggested in the literature rely on time-division-multiplexing of read and write operations based on clocks, or approximations ignoring the reading when coincidental with writing. In this paper, we overcome this challenge and present a clock-less approach wherein reading and writing are performed in different frequency domains. This enables learning and recognition simultaneously on an SNN. We validate our scheme in SPICE circuit simulator by translating a two-layered feed-forward Iris classifying SNN to demonstrate software-equivalent performance. The system performance is not adversely affected by a voltage dependence of conductance in realistic RRAMs, despite departing from linearity. Overall, our approach enables direct implementation of biological SNN algorithms in hardware.

Skyline Computation for Low-Latency Image-Activated Cell Identification

High-throughput label-free single cell screening technology has been studied for noninvasive analysis of various kinds of cells. We tackle the cell identification task in the cell sorting system as a continuous skyline computation. Skyline Computation is a method for extracting interesting entries from a large population with multiple attributes. Jointed rooted-tree (JR-tree) is continuous skyline computation algorithm that manages entries using a rooted-tree structure. JR-tree delays extend the tree to deeper levels to accelerate tree construction and traversal. In this study, we proposed the JR-tree-based parallel skyline computation accelerator. We implemented it on a field-programmable gate array (FPGA). We evaluated our proposed software and hardware algorithms against an existing software algorithm using synthetic and real-world datasets.

New database compression assists in the IBM z14 processor

In this paper, we describe how the IBM z14 processor, together with Db2 for z/OS Version 12, can improve data compression rates and thus reduce data storage requirements and cost for large databases. The new processor improves on the compression hardware accelerator available in earlier IBM Z generations by adding new hardware algorithms that increase the compression ratio and extend the applicability to additional data structures in Db2 for z/OS databases. A new entropy coding step employed after Ziv–Lempel compression reduces the size of data compressed with the prior algorithms by 30% on average. Moreover, the new order-preserving compression algorithm enables database index compression, reducing index sizes by roughly 30%. This results in an overall improvement of 30% of the database size for many applications, with associated benefits in storage requirements, input/output bandwidth, and buffer pool efficiency.

Computational Imaging and Displays: Capturing and displaying richer representations of the world.

Computational imaging techniques allow capturing richer, more complete representations of a scene through the introduction of novel computational algorithms, overcoming the limitations imposed by hardware and optics. The areas of application range from medical imaging to security, to areas in engineering, to name a few. Computational displays combine optics, hardware and computation to faithfully reproduce the world as seen by our eyes, something that current displays still cannot do. This article looks at a few examples of both, aiming to convey the power of the joint co-design of hardware and computational algorithms, also taking into account visual perception.

Fast Scheduling of Robot Teams Performing Tasks With Temporospatial Constraints

The application of robotics to traditionally manual manufacturing processes requires careful coordination between human and robotic agents in order to support safe and efficient coordinated work. Tasks must be allocated to agents and sequenced according to temporal and spatial constraints. Also, systems must be capable of responding on-the-fly to disturbances and people working in close physical proximity to robots. In this paper, we present a centralized algorithm, named “Tercio,” that handles tightly intercoupled temporal and spatial constraints. Our key innovation is a fast, satisficing multi-agent task sequencer inspired by real-time processor scheduling techniques and adapted to leverage a hierarchical problem structure. We use this sequencer in conjunction with a mixed-integer linear program solver and empirically demonstrate the ability to generate near-optimal schedules for real-world problems an order of magnitude larger than those reported in prior art. Finally, we demonstrate the use of our algorithm in a multirobot hardware testbed.

The TOTEM DAQ based on the Scalable Readout System (SRS)

The TOTEM (TOTal cross section, Elastic scattering and diffraction dissociation Measurement at the LHC) experiment at LHC, has been designed to measure the total proton-proton cross-section and study the elastic and diffractive scattering at the LHC energies. In order to cope with the increased machine luminosity and the higher statistic required by the extension of the TOTEM physics program, approved for the LHC’s Run Two phase, the previous VME based data acquisition system has been replaced with a new one based on the Scalable Readout System. The system features an aggregated data throughput of 2GB / s towards the online storage system. This makes it possible to sustain a maximum trigger rate of ∼ 24kHz, to be compared with the 1KHz rate of the previous system. The trigger rate is further improved by implementing zero-suppression and second-level hardware algorithms in the Scalable Readout System. The new system fulfils the requirements for an increased efficiency, providing higher bandwidth, and increasing the purity of the data recorded. Moreover full compatibility has been guaranteed with the legacy front-end hardware, as well as with the DAQ interface of the CMS experiment and with the LHC’s Timing, Trigger and Control distribution system. In this contribution we describe in detail the architecture of full system and its performance measured during the commissioning phase at the LHC Interaction Point.

Analysis of hardware induced receiver synchronization error, caused by differences in manufacturer specific transmission hardware algorithms

With wireless sensor networks having become a tool of choice for a wide range of measurement and monitoring purposes, precise time synchronization is consequentially gaining prominence. Various protocols and synchronization methods are used to achieve the “sweet spot” amongst the accuracy, synchronization speed, and energy consumption of the network. In this paper, we have evaluated the device and modulation specific packet transmission uncertainty, eliminating all possible protocol related uncertainty sources. We have determined that the transceiver hardware dependent time, taken to transmit and receive the packet, not only depends on the transceiver model, but also highly dependent on the modulation. Moreover, sometimes transmission time distribution does not behave per the standard distribution model and seems to be additionally dependent on the internal processing logic of the device. DOI: http://dx.doi.org/10.5755/j01.eie.23.6.13849

A novel algorithm for real-time framework in multiprocessor environment

The objective of the paper is to represent the real-time framework in multiprocessor environment task scheduling process by examining the novel algorithm advanced PSO. The advanced PSO algorithm has the metaphor as the basis to facilitate social interaction, which makes a search on space by making adjustments to the trajectories of individual vectors, referred to "particles" as they are considered as the points that move within the multidimensional search space. This algorithm will reduce the turn-around time, burst time and waiting time for multiprocessor task scheduling, when compared to existing algorithm like first come first served algorithm, shortest job first algorithm and round robin scheduling algorithm. This proposed algorithm is developed and making hardware for tank level water control for single input single output tank system and two input two output tank system. LABVIEW software is used to implement the real-time algorithm in hardware and software. The time taken for searching best position for particles will be executed and compare with all algorithms using bar chart will be given in result.