SVM algorithm oriented for implementation in a low-cost Xilinx FPGA

Abstract

The paper proposes an idea of hardware realization of a space vector modulation (SVM) and transistor commutation method in the direct matrix converter (MC). The presented technique is oriented to an implementation in a single, low-cost programmable logic device (namely, field programmable gate array, FPGA). The SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which drive the large number of power transistors (18 transistors and 18 independent PWM outputs) and “non-standard positions of control pulses” during the switching sequence. Therefore, hardware implementations are becoming popular since computed operations may be executed much faster and more efficiently due to the concurrent nature of the digital devices. In the paper a hardware algorithm of the SVM computation is proposed. Contrary to the existing hardware methods, the presented solution neither requires specialized modeling tools (such as Matlab/Simulink, ISE EDK), nor advanced converters to achieve the hardware representation. It is assumed that the system is prepared in a pure hardware description language (namely, Verilog). Furthermore, the proposed technique permits concurrent execution of most operations. The presented algorithm has been verified experimentally with the low-cost Xilinx FPGAs (in particular, the devices from Artix-7 family). The results of the physical implementation are presented and discussed.