Hardware Algorithms Research Articles

Unsupervised end-to-end training with a self-defined target

Abstract Designing algorithms for versatile AI hardware that can learn on the edge using both labeled and unlabeled data is challenging. Deep end-to-end training methods incorporating phases of self-supervised and supervised learning are accurate and adaptable to input data but self-supervised learning requires even more computational and memory resources than supervised learning, too high for current embedded hardware. Conversely, unsupervised layer-by-layer training, such as Hebbian learning, is more compatible with existing hardware but doesn't integrate well with supervised learning. 
To address this, we propose a method enabling networks or hardware designed for end-to-end supervised learning to also perform high-performance unsupervised learning by adding two simple elements to the output layer: Winner-Take-All (WTA) selectivity and homeostasis regularization. These mechanisms introduce a 'self-defined target' for unlabeled data, allowing purely unsupervised training for both fully-connected and convolutional layers using backpropagation or equilibrium propagation on datasets like MNIST (up to 99.2%), Fashion-MNIST (up to 90.3%), and SVHN (up to 81.5%).
We extend this method to semi-supervised learning, adjusting targets based on data type, achieving 96.6% accuracy with only 600 labeled MNIST samples in a multi-layer perceptron. Our results show that this approach can effectively enable networks and hardware initially dedicated to supervised learning to also perform unsupervised learning, adapting to varying availability of labeled data.

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

Ab-initio tree-tensor-network digital twin for quantum computer benchmarking in 2D

Large-scale numerical simulations of the Hamiltonian dynamics of a noisy intermediate scale quantum computer—a digital twin—could play a major role in developing efficient and scalable strategies for tuning quantum algorithms for specific hardware. Via a two-dimensional tensor network digital twin of a Rydberg atom quantum computer, we demonstrate the feasibility of such a program. In particular, we quantify the effects of gate crosstalks induced by the van der Waals interaction between Rydberg atoms: according to an 8×8 digital twin simulation based on the current state-of-the-art experimental setups, the initial state of a five-qubit repetition code can be prepared with a high fidelity, a first indicator for a compatibility with fault-tolerant quantum computing. The preparation of a 64-qubit Greenberger–Horne–Zeilinger state with about 700 gates yields a 99.9% fidelity in a closed system while achieving a speedup of 35% via parallelization.

Weight‐Reconfigurable Neuromorphic Computing Systems for Analog Signal Integration

AbstractOwing to the necessity of high computation amounts has emerged, interest in a neuromorphic computing system has significantly increased as a compelling alternative to conventional CMOS technology. This paper presents a neuromorphic hardware algorithm to finely reconfigure multi‐input signal processing, which can be implemented as an advanced processor for diverse external information, and the hydrogen explosion risk assessment system is demonstrated as a proof of concept. Hydrogen concentration and temperature are used as sensory inputs for the signal integration and the precise values of them are determined by offsetting the effect of temperature on the electrical signal from the hydrogen sensor through a sensor circuit. Each signal is then updated by the weight control circuit and converted into a postsynaptic current to represent the hydrogen explosion risk using a multi‐input artificial synapse. This simplicity of the circuitry renders the fabrication of all components and circuits compatible with simple inkjet printing methods, enabling cost‐effective and high‐throughput manufacturing. Additionally, the real‐time demonstration of the neuromorphic computing system is successfully conducted, offering insights into the practical application of neuromorphic computing.

A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic

The purpose of the paper is to propose a new implementation of the PID (proportional–integral–derivative) algorithm in digital hardware. The proposed structure is optimized for cost. It follows a serialized, rather than parallel, scheme. It uses only one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequentially cyclic manner. The proposed circuit operates on standard single-precision (32-bit) floating-point numbers. It implements an extended PID formula, containing a non-ideal derivative component, and weighting coefficients, which enable reducing the influence of setpoint changes in the proportional and derivative components. The circuit was implemented in a Cyclone V FPGA (Field-Programmable Gate Array) device from Intel, Santa Clara, CA, USA. The proper operation of the circuit was verified in a simulation. For the specific implementation, which is reported in the paper, the sampling period of 516 ns was obtained, which means that the proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on single-precision floating-point numbers. However, the presented solution is much more efficient in terms of cost. It uses 1173 LUT (Look-up Table) blocks, 1026 registers, and 1 DSP (Digital Signal Processing) block, i.e., about 30% of logic resources required by comparable solutions.

Hardware algorithm design and validation for nuclear radiation imaging based on Monte Carlo simulation

The nuclear radiation imaging technology, aimed at illustrating the position and distribution of radioactive sources, has undergone extensive research. By relying on a simulated radiation imaging system for data acquisition, we can significantly expedite the development cycle of these imaging instruments. Establishing simulated experimental scenarios and radiation imaging systems is of paramount significance in obtaining output signals for algorithmic testing and validation. This study is divided into two parts: simulation and hardware algorithm. In the simulation part, precise simulation of scintillation light transport in a crystal was achieved using the GEANT4 Monte Carlo simulation toolkit. A LaBr3(Ce) detector system was simulated by digitizing photon interactions. In the hardware algorithm part, a positioning algorithm based on a fully connected neural network was implemented and optimized using a heterogeneous distributed storage approach. The system validated and assessed the FPGA-based neural network gamma camera positioning algorithm, demonstrating significant consistency with computer-generated images in capturing the shape and dispersion of radioactive sources (planar, multi-point, and ring-shaped).

Simulation of a Diels-Alder reaction on a quantum computer.

The simulation of chemical reactions is an anticipated application of quantum computers. Using a Diels-Alder reaction as a test case, in this study we explore the potential applications of quantum algorithms and hardware in investigating chemical reactions. Our specific goal is to calculate the activation barrier of a reaction between ethylene and cyclopentadiene forming a transition state. To achieve this goal, we use quantum algorithms for near-term quantum hardware (entanglement forging and quantum subspace expansion) and classical post-processing (many-body perturbation theory) in concert. We conduct simulations on IBM quantum hardware using up to 8 qubits, and compute accurate activation barrier in the reaction between cyclopentadiene and ethylene by accounting for both static and dynamic electronic correlation. This work illustrates a hybrid quantum-classical computational workflow to study chemical reactions on near-term quantum devices, showcasing the potential for performing quantum chemistry simulations on quantum hardware to predict activation barriers in agreement with those predicted by CASCI.

High-Speed Phase Structured Light Integrated Architecture on FPGA

Phase-shifting fringe projection profilometry (FPP) in three-dimension (3D) structured light measurement is widely applied in high-accuracy 3D shape measurement scenarios. But motion objects or other dynamic scenarios make the traditional phase-shifting FPP hard to deal with due to its sizable CPU-based execution time. Therefore, an embedded high-speed and high-accuracy phase-shifting FPP system is designed and implemented on FPGAs. The system implements a three-frequency four-step phase-shifting hardware algorithm with RTL-level caching, multi-frame image ping-pong buffering, and data handling, etc. The system exhibits fully-parallel and pipeline processing while behaving with lower resource and power consumption. Measurement experiments indicate that the proposed method can reach high-accuracy real-time 3D shape measurement with a 3D decoding speed of 40.15 fps when the clock frequency is 200MHz, and the image size is 2432×2048.

Memristive Monte Carlo DropConnect crossbar array enabled by device and algorithm co-design.

Device and algorithm co-design aims to develop energy-efficient hardware that directly implements complex algorithms and optimizes algorithms to match the hardware's characteristics. Specifically, neuromorphic computing algorithms are constantly growing in complexity, necessitating an ongoing search for hardware implementations capable of handling these intricate algorithms. Here, we present a memristive Monte Carlo DropConnect (MC-DC) crossbar array developed through a hardware algorithm co-design approach. To implement the MC-DC neural network, stochastic switching and analog memory characteristics are required, and we achieved them using Ag-based diffusive selectors and Ru-based electrochemical metalization (ECM) memristors, respectively. The devices were integrated with a one-selector one-memristor (1S1M) structure, and their well-matched operating voltages and currents enabled stochastic readout and deterministic analog programming. With the integrated hardware, we successfully demonstrated the MC-DC operation. Additionally, the selector allowed for the control of switching polarity, and by understanding this hardware characteristic, we were able to modify the algorithm to fit it and further improve the network performance.

SIMULATION MODEL OF AN ADARTIVE DIGITAL FILTER BASED ON THE LEAST SQUARES METHOD

In accordance with contemporary requirements in the fields of mobile and embedded telecommunications and electronics, there is a growing need for faster, smaller, and energy-efficient digital electronic devices (DEDs). These devices include microcontrollers, digital signal processors, and programmable logic integrated circuits (FPGAs).
 Utilizing DEDs involves the hardware execution of advanced digital signal processing (DSP) algorithms tailored to the specific architecture of the electronic device. To expedite the design process when directly implementing DSP algorithms in hardware, simulation models are generated to facilitate optimizing the design during the creation of the programming component for FPGAs.
 The paper discusses the outcomes of an investigation into an adaptive filter (AF) model that relies on the recursive least squares method (RLS). During the simulation, an analysis of the time and frequency parameters of the AF model was conducted. It was determined that the quality of the filtering process reaches a plateau at the 28th order, and further increasing the AF order does not lead to a significant improvement in signal filtering. Instead, it results in an increased demand for hardware resources. Furthermore, during the verification of the proposed simulation model, an AF-based noise reduction system was simulated. The total harmonic distortion (THD) level for the built-in AF unit was found to be 1.05 % that serves as confirmation of the effectiveness of the developed AF unit.
 Therefore, through this investigation, the most suitable order for the AF has been identified. This choice will enable a more effective utilization of FPGA resources when implementing the AF in hardware. The study results validate the accuracy and effectiveness of the hardware-centric simulation model developed, while also demonstrating the hardware-oriented architecture of the adaptive RLS filter for its forthcoming implementation on FPGA.

Research of the system-on-chip-based relay protection technology

The relay protection device is the core equipment that ensures the safe and stable operation of a power grid. With the open access of a large number of distributed generation, DC transmission and electric vehicles, a new deep low-carbon power system dominated by power electronic devices has gradually been formed. It is difficult for the traditional control and protection architecture, methods, and technology to meet the business characteristics and functional requirements of a diversified interaction, agile response, safety, and credibility of the power grid in the future. This paper presents a chip-based relay protection technology based on system-on-chip (SoC), which is described from four aspects, namely, the architectural design of the relay protection SoC, software and hardware cooperative relay protection based on the SoC IP core, experimental verification, and engineering application. The results show that the relay protection SoC proposed in this paper has significantly improved the performance of high-speed data acquisition and interaction through hardware algorithm engine acceleration and software and hardware collaborative computing, which is helpful to realize the local equipment operation and the integration of primary and secondary equipment, shorten the protection action time, and improve the speed, reliability, and stability of relay protection devices.

A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking

Although advances in event-based machine vision algorithms have demonstrated unparalleled capabilities in performing some of the most demanding tasks, their implementations under stringent real-time and power constraints in edge systems remain a major challenge. In this work, a reconfigurable hardware-software architecture called REMOT, which performs real-time event-based multi-object tracking on FPGAs, is presented. REMOT performs vision tasks by defining a set of actions over attention units (AUs). These actions allow AUs to track an object candidate autonomously by adjusting its region of attention and allow information gathered by each AU to be used for making algorithmic-level decisions. Taking advantage of this modular structure, algorithm-architecture codesign can be performed by implementing different parts of the algorithm in either hardware or software for different tradeoffs. Results show that REMOT can process 0.43–2.91 million events per second at 1.75–5.45 W. Compared with the software baseline, our implementation achieves up to 44 times higher throughput and 35.4 times higher power efficiency. Migrating the Merge operation to hardware further reduces the worst-case latency to be 95 times shorter than the software baseline. By varying the AU configuration and operation, a reduction of 0.59–0.77 mW per AU on the programmable logic has also been demonstrated.

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

AbstractThe continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage.

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application.

A high-performance Driver State Monitoring (DSM) application for the detection of driver drowsiness is presented in this paper. The popular Ensemble of Regression Trees (ERTs) machine learning method has been employed for the alignment of 68 facial landmarks. Open-source implementation of ERTs for facial shape alignment has been ported to different platforms and adapted for the acceleration of the frame processing speed using reconfigurable hardware. Reducing the frame processing latency saves time that can be used to apply frame-to-frame facial shape coherency rules. False face detection and false shape estimations can be ignored for higher robustness and accuracy in the operation of the DSM application without sacrificing the frame processing rate that can reach 65 frames per second. The sensitivity and precision in yawning recognition can reach 93% and 97%, respectively. The implementation of the employed DSM algorithm in reconfigurable hardware is challenging since the kernel arguments require large data transfers and the degree of data reuse in the computational kernel is low. Hence, unconventional hardware acceleration techniques have been employed that can also be useful for the acceleration of several other machine learning applications that require large data transfers to their kernels with low reusability.

Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning.

Equilibrium propagation (EP) has been proposed recently as a new neural network training algorithm based on a local learning concept, where only local information is used to calculate the weight update of the neural network. Despite the advantages of local learning, numerical iteration for solving the EP dynamic equations makes the EP algorithm less practical for realizing edge intelligence hardware. Some analog circuits have been suggested to solve the EP dynamic equations physically, not numerically, using the original EP algorithm. However, there are still a few problems in terms of circuit implementation: for example, the need for storing the free-phase solution and the lack of essential peripheral circuits for calculating and updating synaptic weights. Therefore, in this paper, a new analog circuit technique is proposed to realize the EP algorithm in practical and implementable hardware. This work has two major contributions in achieving this objective. First, the free-phase and nudge-phase solutions are calculated by the proposed analog circuits simultaneously, not at different times. With this process, analog voltage memories or digital memories with converting circuits between digital and analog domains for storing the free-phase solution temporarily can be eliminated in the proposed EP circuit. Second, a simple EP learning rule relying on a fixed amount of conductance change per programming pulse is newly proposed and implemented in peripheral circuits. The modified EP learning rule can make the weight update circuit practical and implementable without requiring the use of a complicated program verification scheme. The proposed memristor conductance update circuit is simulated and verified for training synaptic weights on memristor crossbars. The simulation results showed that the proposed EP circuit could be used for realizing on-device learning in edge intelligence hardware.

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances.

A Hardware-Based Configurable Algorithm for Eye Blink Signal Detection Using a Single-Channel BCI Headset.

Eye blink artifacts in electroencephalographic (EEG) signals have been used in multiple applications as an effective method for human-computer interaction. Hence, an effective and low-cost blinking detection method would be an invaluable aid for the development of this technology. A configurable hardware algorithm, described using hardware description language, for eye blink detection based on EEG signals from a one-channel brain-computer interface (BCI) headset was developed and implemented, showing better performance in terms of effectiveness and detection time than manufacturer-provided software.

Polarized laser target detection system for smoky environment based on full-waveform decomposition and multiscale convolutional neural networks with attention

To overcome the problem that the smoky environment affects the laser detection performance and generates false alarm, this paper proposes a polarization pulse laser target detection method based on the difference of the polarization information between the target and the smoke, combining full waveform decomposition and Multiple Scale-Attention convolutional neural network with Focal loss function (MSAFCNN). Optimal parameters of the algorithm are obtained by studying the recognition accuracy of the algorithm with different sampling rates and the number of convolution kernels. The polarization pulse laser detection platform is built and the target detection experiments under five different scenarios using infrared lasers are conducted. The polarization echo signals of the smoke and the targets are collected and the recognition accuracy of the proposed algorithm is calculated. The ablation experiments are carried out and MSAFCNN is compared with several advanced algorithms. The experimental results show that the proposed algorithm has the highest recognition accuracy (99.085% ± 0.249%) compared with other algorithms. According to the ablation experiment, the recognition accuracy can be improved by 1.381% using MSAFCNN. The recognition experiments with different sampling rates and numbers of convolutional kernels are performed, and the accuracy of the proposed algorithm can reach 99.348% ± 0.178% at 1 GHz sampling rate and 98.910% ± 0.297% at 500 MHz sampling rate. The optimal number of convolutional kernels is 16, and the number of the algorithm parameters is only 125.273 KB, which provides the feasibility for the subsequent implementation of the algorithm in hardware.

Hybrid stochastic synapses enabled by scaled ferroelectric field-effect transistors

Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work, we leverage the stochastic switching of a three-state ferroelectric field-effect transistor to implement a long-term and short-term two-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scaled 28 nm high-k metal gate technology-based device to develop a probabilistic model of the hybrid stochastic synapse. In addition to the advantage of ultra-low programming energies afforded by scaling, our hardware–algorithm co-design analysis reveals the efficacy of the two-tier memory in comparison to binary stochastic synapses in on-chip learning tasks—paving the way for algorithms exploiting multi-state devices with probabilistic transitions beyond deterministic ones.

Barnes–Hut approximation based accelerating t-SNE for seizure detection

Background:Automatic detection of epileptic seizures is critical in the paradigm of epilepsy diagnosis and in relieving the cumbersome visual inspection of electroencephalogram (EEG) recordings. A speedy algorithm could help in more reliable monitoring and detection of seizures. Methods and materials:In this study, we aim to provide an EEG-based seizure detection system with computational efficiency and improved performance. In the proposed work, many features including temporal, spectral, and non-linear features from each intrinsic mode function (IMF) of empirical mode decomposition (EMD) have been used. Barnes–Hut approximation-based t-stochastic neighborhood embedding (bh t-SNE) was explored for the first time to observe the reduction in computational time (CT) period in the automatic seizure detection system. Three classes of widely-used EEG Bonn datasets were used to assess the performance of the proposed method. Results:The proposed Barnes–Hut-based accelerating t-SNE along with SVM and KNN reduced more than half of the classification time with the same accuracy. The classifier takes 2.147±0.1 s for SVM and 1.216±0.1 s for KNN without the proposed t-SNE and 1.31±0.1 s for SVM and 0.736±0.1 s for KNN (at the trade-off parameter θ=0.5) with the proposed Barnes–hut based t-SNE (bh t-SNE) at an accuracy of 100%. Conclusions: The findings of the experimental work indicate that the proposed method is effective in reducing the computational time while maintaining the required efficacy. As a result, the inclusion of these algorithms in hardware might prove to be effective in assisting neurologists in detecting seizures.