Abstract
In accordance with contemporary requirements in the fields of mobile and embedded telecommunications and electronics, there is a growing need for faster, smaller, and energy-efficient digital electronic devices (DEDs). These devices include microcontrollers, digital signal processors, and programmable logic integrated circuits (FPGAs).
 Utilizing DEDs involves the hardware execution of advanced digital signal processing (DSP) algorithms tailored to the specific architecture of the electronic device. To expedite the design process when directly implementing DSP algorithms in hardware, simulation models are generated to facilitate optimizing the design during the creation of the programming component for FPGAs.
 The paper discusses the outcomes of an investigation into an adaptive filter (AF) model that relies on the recursive least squares method (RLS). During the simulation, an analysis of the time and frequency parameters of the AF model was conducted. It was determined that the quality of the filtering process reaches a plateau at the 28th order, and further increasing the AF order does not lead to a significant improvement in signal filtering. Instead, it results in an increased demand for hardware resources. Furthermore, during the verification of the proposed simulation model, an AF-based noise reduction system was simulated. The total harmonic distortion (THD) level for the built-in AF unit was found to be 1.05 % that serves as confirmation of the effectiveness of the developed AF unit.
 Therefore, through this investigation, the most suitable order for the AF has been identified. This choice will enable a more effective utilization of FPGA resources when implementing the AF in hardware. The study results validate the accuracy and effectiveness of the hardware-centric simulation model developed, while also demonstrating the hardware-oriented architecture of the adaptive RLS filter for its forthcoming implementation on FPGA.
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